Growth-direction-dependent characteristics of Ge-on-insulator by Si–Ge mixing triggered melting growth

The lateral liquid-phase epitaxy of Ge-on-insulator (GOI) using Si seeds has been investigated as a function of the Si-seed orientation and the growth direction. Giant single-crystalline GOI structures with ∼200 μm length are obtained using Si(1 0 0), (1 1 0), and (1 1 1) seeds. The very long growth is explained on the basis of the solidification temperature gradient due to Si-Ge mixing around the seeding area and the thermal gradient due to the latent heat around the solid/liquid interface at the growth front. In addition, growth with rotating crystal orientations is observed for samples with several growth directions. The rotating growth is explained on the basis of the bonding strength between lattice planes at the growth front. This rotating growth does not occur in any direction for (1 0 0) orientated seeds. Based on this finding the mesh-patterned GOI growth with a large area (250 μm × 500 μm) is demonstrated.     

Subband structure and effective mass of relaxed and strained Ge (1 1 0) PMOSFETs

Effective mass and mobility of strained Ge (1 1 0) inversion layer in PMOSFET are studied theoretically in this paper. The strain condition considered in the calculations is the intrinsic strain resulting from growing the Ge layer on the (1 1 0) Si substrate. The quantum confinement effect resulting from the vertical effective electric field is incorporated into the k · p calculation. Various effective masses, such as quantization effective mass, m_z, density of states effective mass, m_DOS, and conductivity mass, m_C, as well as the hole mobility of strained Ge (1 1 0) inversion layer for PMOS under substrate strain and various effective electric field strengths are all investigated.     

Low threading dislocation density Ge deposited on Si (1 0 0) using RPCVD

Epitaxial Ge layer growth of low threading dislocation density (TDD) and low surface roughness on Si (1 0 0) surface is investigated using a single wafer reduced pressure chemical vapor deposition (RPCVD) system. Thin seed Ge layer is deposited at 300 °C at first to form two-dimensional Ge surface followed by thick Ge growth at 550 °C. Root mean square of roughness (RMS) of ∼0.45 nm is achieved. As-deposited Ge layers show high TDD of e.g. ∼4 × 10⁸ cm⁻² for a 4.7 μm thick Ge layer thickness. The TDD is decreasing with increasing Ge thickness. By applying a postannealing process at 800 °C, the TDD is decreased by one order of magnitude. By introducing several cycle of annealing during the Ge growth interrupting the Ge deposition, TDD as low as ∼7 × 10⁵ cm⁻² is achieved for 4.7 μm Ge thick layer. Surface roughness of the Ge sample with the cyclic annealing process is in the same level as without annealing process (RMS of ∼0.44 nm). The Ge layers are tensile strained as a result of a higher thermal expansion coefficient of Ge compared to Si in the cooling process down to room temperature. Enhanced Si diffusion was observed for annealed Ge samples. Direct band-to-band luminescence of the Ge layer grown on Si is demonstrated.     

Fully depleted silicon on insulator MOSFETs on (1 1 0) surface for hybrid orientation technologies

Effective memory performance of the nonvolatile memory/thin film transistor (NVM/TFT) devices needs good TFT characteristics. The reduction in leakage current of the TFT devices was accomplished with the gate offset (GOF) structure. A simplified fabrication process for the GOF NVM is introduced in this study using the insulator over-etching approach. Nonvolatile memory devices on glass using SiO₂/SiO_x/SiO_xN_y stack with an offset length of 0, 0.2, 0.4, and 0.6 μm were investigated. The highly selective etching process and the short offset length help to avoid the problem of the gate aluminum collapsing on the source/drain electrodes. The TFT characteristics of the GOF structures displayed the remarkable improvement in leakage from 1.1 × 10⁻¹¹ A, for the TFT without an offset region, to the low OFF current of 1.34 × 10⁻¹² A for the device with a 0.6 μm offset length. The longer offset length gave the lowest OFF current. The degradation in transconductance and the threshold voltage was negligible with the g_m values of about 3 × 10⁻⁶ S and ΔV_th of about 0.2 V, respectively. The switching characteristics remained similar for all the devices. Additionally, the GOF structures slightly enhanced the retention characteristics. The memory window of the NVM without the offset after a retention time of 10,000 s was 58%, lower than the over 69% of the GOF devices. Therefore, the application of the GOF structure to reduce the leakage of the NVM/TFT proved to be effective.     

X-ray microdiffraction investigation of crystallinity and strain relaxation in Ge thin lines selectively grown on Si(0 0 1) substrates

We used X-ray microdiffraction (XRMD) to investigate the crystallinity and strain relaxation of Ge thin lines with widths of 100, 200, 500 and 1000 nm selectively grown on Si(0 0 1) substrates using a patterned SiO₂ mask by chemical vapor deposition. The variations of the strain relaxation in the line and width directions were also investigated in Ge thin lines with a width of 100 nm. After growth, crystal domains with very small tilt angles were detected in Ge lines with all four line widths. The tilt angle range was larger in thinner Ge lines. After annealing at 700 °C, the formation of a single, large domain with a specific tilt angle was detected by XRMD for Ge thin lines with widths of 100 and 200 nm. These experimental results reflect the effects of SiO₂ side walls around the Ge thin lines on crystallinity and strain relaxation of Ge.     

Over 1000 V/30 mA operation GaN-on-Si MOSFETs fabricated on Si substrates

We demonstrated the operation of GaN-on-Si metal-oxide-semiconductor field effect transistors (MOSFETs) for power electronics components. The interface states at SiO₂/GaN were successfully improved by annealing at 800 °C for 30 min in N₂ ambient. The interface state density was less than 1 × 10¹¹ cm^-2 eV⁻¹ at E_c − 0.4 eV. The n⁺ contact layers as the source and drain regions as well as the reduced surface field (RESURF) zone were formed using a Si ion implantation technique with the activation annealing at 1200 °C for 10 s in rapid thermal annealing (RTA). As a result, we achieved an over 1000 V and 30 mA operation on GaN-on-Si MOSFETs. The threshold voltage was +2.6 V. It was found that the breakdown voltage depended upon the RESURF length and nitride based epi-layer thickness. In addition, we discussed the comparison of each performance of GaN-on-Si with -sapphire devices.     

Effect of dimensional parameters on the current of MSM photodetector

In this work, we present the influence of dimensional parameters on dark current and photocurrent of the metal-semiconductor-metal photodetector (MSM). MSM photodetectors of different sizes have been fabricated on GaAs (NID). The active area of MSM samples varies between 1×1 μm² and 10×10 μm² with equal electrodes spacing and finger widths (l=D) varying between 0.2 and 1 μm. The I(V) characterization in inverse and direct polarization in darkness shows good symmetry of curves, which shows the good performance of components and successful fulfillment of the Schottky contacts. The application of laser fiber of incident light power of 16 mW at wavelength of 850 nm for the illumination of the MSM photodetectors showed the evolution of the photocurrent ranging from 0.75 to 1.81 mA, respectively, for 1 to 0.2 μm electrodes spacing at 3 V and active area S=3×3 μm². We showed also that variation ranging from 0.45 to 2.5 mA, respectively, for S=1×1 μm² to S=10×10 μm² at 3 V and 0.3 μm electrodes spacing. The resistance of MSM photodetectors obtained evolved proportionally to the electrodes spacing (0.87 kΩ for D=0.2 μm and 2.27 kΩ for D=1 μm with S=3×3 μm²) and inversely proportional to the surface area (2.02 kΩ for S=1×1 μm², and 0.56 kΩ for S=10×10 μm² with 0.3 μm inter electrodes spacing).     

Nanoscale FeS2 (Pyrite) as a Sustainable Thermoelectric Material

We have synthesized undoped, Co-doped (up to 5%), and Se-doped (up to 4%) FeS₂ materials by mechanical alloying in a planetary ball mill and investigated their thermoelectric properties from room temperature (RT) to 600 K. With decreasing particle size, the undoped FeS₂ samples showed higher electrical conductivity, from 0.02 S cm^?1 for particles with 70 nm grain size up to 3.1 S cm^?1 for the sample with grain size of 16 nm. The Seebeck coefficient of the undoped samples showed a decrease with further grinding, from 128 μV K^?1 at RT for the sample with 70-nm grains down to 101 μV K^?1 for the sample with grain size of 16 nm. The thermal conductivity of the 16-nm undoped sample lay within the range from 1.3 W m^?1 K^?1 at RT to a minimal value of 1.2 W m^?1 K^?1 at 600 K. All doped samples showed improved thermoelectric behavior at 600 K compared with the undoped sample with 16 nm particle size. Cobalt doping modified the p-type semiconducting behavior to n-type and increased the thermal conductivity (2.1 W m^?1 K^?1) but improved the electrical conductivity (41 S cm^?1) and Seebeck coefficient (-129 μV K^?1). Isovalent selenium doping led to a slightly higher thermal conductivity (1.7 W m^?1 K^?1) as well as to an improved electrical conductivity (26 S cm^?1) and Seebeck coefficient (110 μV K^?1). The ZT value of FeS₂ was increased by a factor of five by Co doping and by a factor of three by Se doping.     

Thermal measurements and analysis of AlGaInP/GaInP MQW red LEDs with different chip sizes and substrate thicknesses

Thermal properties of AlGaInP/GaInP MQW red LEDs are investigated by thermal measurements and analysis for different chip sizes and substrate thicknesses. To extract the thermal resistance (R_th), junction temperature (T_j) is experimentally determined by both forward voltage and electroluminescence (EL) emission peak shift methods. For theoretical thermal analysis, thermal parameters are calculated in simulation using measured heat source densities. The T_j value increases with increasing the injection current, and it decreases as the chip size becomes larger. The use of a thin substrate improves the heat removal capability. At 450 mA, the T_j values of 315 K and 342 K are measured for 500 × 500 μm² LEDs with 110 μm and 350 μm thick substrates, respectively. For 500 × 500 μm² LEDs with 110 μm thick substrate, the R_th values of 13.99 K/W and 14.89 K/W are obtained experimentally by the forward voltage and EL emission peak shift methods, respectively. The theoretically calculated value is 13.44 K/W, indicating a good agreement with the experimental results.     

RF power performance evaluation of surface channel diamond MESFETs

We experimentally investigate the large-signal radio frequency performances of surface-channel p-type diamond MESFETs fabricated on hydrogenated polycrystalline diamond. The devices under examination have a coplanar layout with two gate fingers, total gate periphery of 100 μm; in DC they exhibit a hole accumulation behavior with threshold voltage V_t ≈ 0-0.5 V and maximum drain current density of 120 mA/mm. The best small-signal radio frequency performances (maximum cutoff or transition frequency f_T and oscillation frequency f_max) were obtained close to the threshold and were of the order of 6 and 15 GHz, respectively. The power radio frequency response was characterized by driving the devices in class A at an operating frequency of 2 GHz and identifying through the active load-pull technique the optimum load for maximum power added efficiency. A power gain in linearity of 8 dB and an output power of approximately 0.2 W/mm with 22% power added efficiency were obtained on the optimum load impedance at a bias point V_DS = −14 V, V_GS = −1 V. To the best of our knowledge, these are the first large signal measurements ever reported for surface MESFET on polycrystalline diamond, and show the potential of such technology for the development of microwave power devices.     

Structural advantages of rectangular-like channel cross-section on electrical characteristics of silicon nanowire field-effect transistors

We have experimentally demonstrated structural advantages due to rounded corners of rectangular-like cross-section of silicon nanowire (SiNW) field-effect transistors (FETs) on on-current (I_ON), inversion charge density normalized by a peripheral length of channel cross-section (Q_inv) and effective carrier mobility (μ_eff). The I_ON was evaluated at the overdrive voltage (V_OV) of 1.0 V, which is the difference between gate voltage (V_g) and the threshold voltage (V_th), and at the drain voltage of 1.0 V. The SiNW nFETs have revealed high I_ON of 1600 μA/μm of the channel width (w_NW) of 19 nm and height (h_NW) of 12 nm with the gate length (L_g) of 65 nm. We have separated the amount of on-current per wire at V_OV = 1.0 V to a corner component and a flat surface component, and the contribution of the corners was nearly 60% of the total I_ON of the SiNW nFET with L_g of 65 nm. Higher Q_inv at V_OV = 1.0 V evaluated by advanced split-CV method was obtained with narrower SiNW FET, and it has been revealed the amount of inversion charge near corners occupied 50% of all the amount of inversion charge of the SiNW FET (w_NW = 19 nm and h_NW = 12 nm). We also obtained high μ_eff of the SiNW FETs compared with that of SOI planar nFETs. The μ_eff at the corners of SiNW FET has been calculated with the separated amount of inversion charge and drain conductance. Higher μ_eff around corners is obtained than the original μ_eff of the SiNW nFETs. The higher μ_eff and the large fractions of I_ON and Q_inv around the corners indicate that the rounded corners of rectangular-like cross-sections play important roles on the enhancement of the electrical performance of the SiNW nFETs.     

Determination of the laterally homogeneous barrier height of palladium Schottky barrier diodes on n-Ge (1 1 1)

We have studied the experimental linear relationship between barrier heights and ideality factors for palladium (Pd) on bulk-grown (1 1 1) Sb-doped n-type germanium (Ge) metal-semiconductor structures with a doping density of about 2.5×10¹⁵ cm^?3. The Pd Schottky contacts were fabricated by vacuum resistive evaporation. The electrical analysis of the contacts was investigated by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements at a temperature of 296 K. The effective barrier heights from I–V characteristics varied from 0.492 to 0.550 eV, the ideality factor n varied from 1.140 to 1.950, and from reverse bias capacitance–voltage (C^?2–V) characteristics the barrier height varied from 0.427 to 0.509 eV. The lateral homogenous barrier height value of 0.558 eV for the contacts was obtained from the linear relationship between experimental barrier heights and ideality factors. Furthermore the experimental barrier height distribution obtained from I–V and (C^?2?V) characteristics were fitted by Gaussian distribution function, and their mean values were found to be 0.529 and 0.463 eV, respectively.     

High photosensitivity and low dark current of photoconductive semiconductor switch based on ZnO single nanobelt

Photoconductive semiconductor switch (PCSS) based on ZnO single nanobelt (NB) was fabricated by controlling the concentration of mixed solution and using the probe technique, and applied into a test circuit to control the circuit state. The current-voltage characteristics and voltage spectra were investigated by system source meter and oscillograph, and the results show that the PCSS is of high photosensitivity of ∼10⁴, low dark current of ∼10⁻³ μA, low power consumption of ∼2.45 μW, typical rise time 0.12 s, and decay time 0.15 s. Within the wavelength range of 280-340 nm, the shorter the wavelength is, the higher the voltage response is. The test circuit state conversion between “1” and “0” is obviously corresponding to UV illumination “on” and “off”. The high photosensitivity and low dark current of PCSS can be reasonably explained by using the view point of light absorption and oxygen chemisorption mechanism.     

Growth of epitaxial Pr2O3 layers on Si(1 1 1)

The growth of Pr₂O₃ layers on Si(1 1 1) has been studied by X-ray diffraction, Low-energy electron diffraction (LEED) and atomic force microscopy (AFM). Pr₂O₃ starts to grow as a 0.6-nm thick layer corresponding to one unit cell of the hexagonal phase (1 ML). The X-ray results indicate that layers thicker than 0.6 nm do not grow with the hexagonal phase. Growth takes place at a sample temperature of 500–550 °C. Annealing of the monolayer in UHV at a temperature above 700 °C leads to the formation of Pr₂O₃ and PrSi₂ islands. Silicide islands are found only at annealing in UHV and do not occur at annealing in oxygen atmosphere of 10⁻⁸ mbar. The LEED pattern after heating to 730 °C shows a (2×2) and (√3×√3) superstructure and after heating to 1000 °C a (1×5) superstructure occurs. The superstructures seen in the LEED pattern arise from silicide structures in the area between the islands. The silicide remains on the surface and cannot be removed with flashing to 1100 °C. Further deposition of Pr₂O₃ on the surface covered with silicide phases does not lead to growth of ordered layers.     

Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology

In this paper, we have studied the effect of systematic downscaling of MOS channel length of the performance of the hybrid GaN MOS-HEMT with numerical simulations. The improvement in on-state conduction, together with concomitant short channel effects, including drain induced barrier lowering (DIBL) is quantitatively evaluated. A specific on-resistance of 2.1 mΩ cm² has been projected for a MOS channel length of 0.38 μm. We also have assessed the impact of high-k gate dielectrics, such as Al₂O₃. In addition, we have found that adding a thin GaN cap layer on top of AlGaN barrier can help reducing short channel effects.     

Performance enhancement in Ge pMOSFETs with <1 0 0> orientation fabricated with a Si-compatible process flow

The electrical characterization of Ge pMOSFETs having <1 1 0> and <1 0 0> orientations with gate lengths of 3 μm have been demonstrated with a Si-compatible process flow. Employment of <1 0 0> orientation in Ge pMOSFETs without incorporation of strain provided ∼10% enhancement in effective hole mobility and drive current when compared to <1 1 0> oriented regular transistors. In this fabrication technology, the effective hole mobility improves from 190 cm²/V s for <1 1 0> devices to 210 cm²/V s for the <1 0 0> oriented Ge devices at room temperature, which is ∼2 times the hole mobility of Si pFET devices. This study also presents first time investigation of post metallization anneal (PMA) at 350 °C in H₂ ambient for <1 0 0> Ge pMOSFETs. The overall performance of the devices has been enhanced by 15% after performing PMA. It is likely attributed to a strong decrease of D_it, improving the transistor performance. These results indicate that the <1 0 0> Ge pMOSFETs could be a viable candidate for future low voltage high speed CMOS applications.     

Double-polysilicon SiGe HBT architecture with lateral base link

We present an analysis of a modified double-polysilicon SiGe:C HBT module showing a CML ring oscillator gate delay τ_D of 2.5 ps, and f_T/f_max/BV_CEo values of 300 GHz/350 GHz/1.85 V (Fox et al., 2008) [1]. A key feature of the HBT module is a connection of the extrinsic and intrinsic base regions by lateral epitaxial overgrowth, which aims to overcome the limits of the conventional double-polysilicon architecture in simultaneously reducing R_B and C_BC. Potential benefits and barriers of the proposed device structure on the way to higher performance are reviewed with regard to the recently demonstrated performance gain of the classical double-polysilicon approach. The paper addresses technological challenges one is faced when the here presented device structure is scaled to minimum device dimensions.     

Electrical characterization of thiols self-assembled layers on GaP (1 1 1) structures

The experimental studies on III–V semiconductor compounds surface passivation phenomena are mainly dedicated to solve some technological problems as those regarding the ways to keep the chemical stability of native oxides on surfaces. Self-assembled monolayers (SAMs) provide a simple way to produce relatively ordered structures at a molecular scale, which seems to be capable to protect the clean surface against the evolution of oxidation process. In this respect, thin films of SAMs of aliphatic thiol (dodencanthiol—CH₃(CH₂)₁₁SH) and aromatic thiol (4, 4′ tiobisbenzenthiol-S (C₆H₄SH)₂ have been deposited on the surface of GaP (1 1 1) samples. The electrical properties measurements of some structures based on GaP compound was performed. There were recorded current–voltage (I–V) characteristics for complex structures AuGeNi/R-SH/GaP and AuGeNi/Ar-SH/GaP in darkness and also exposed to a Xe lamp. In dark and in “reverse bias” way, the I–V characteristics present the feature of a Zenner diode for GaP/Ar-SH and a gradual increase of current for GaP/R-SH. In dark and “in forward bias” way, the current increases as for a normal diode for both GaP/Ar-SH and GaP/R-SH structures. The complex structures (e.g.: In/AuGeNi/R-SH/GaP/R-SH/AuGeNi/In) are less sensitive to light. The SEM analysis performed on a GaP/R-SH surface shows a continuous packed up layer while GaP/Ar-SH looks like an inhomogeneous deposition of layers with different thickness regions. The diodes’ ideality factors determined from I–V characteristics are unusually high (n2) as a possible result of inhomogeneous Schottky contacts or due to ageing effects, in the field of degradation.     

Growth temperature dependence of epitaxial Gd2O3 films on Si(1 1 1)

This article reports on the epitaxy of crystalline high κ oxide Gd₂O₃ layers on Si(1 1 1) for CMOS gate application. Epitaxial Gd₂O₃ thin films have been grown by Molecular Beam Epitaxy (MBE) on Si(1 1 1) substrates between 650 and 750 °C. The structural and electrical properties were investigated depending on the growth temperature. The C–V measurements reveal that equivalent oxide thickness (EOT) equals 0.7 nm for the sample deposited at the optimal temperature of 700 °C with a relatively low leakage current of 3.6 × 10^?2 A/cm² at |V_g ? V_FB| = 1 V.     

Epitaxial growth of Dy2O3 thin films on epitaxial Dy-germanide films on Ge(0 0 1) substrates

Ultra-thin films of Dy are grown on Ge(0 0 1) substrates by molecular beam deposition near room temperature and immediately annealed for solid phase epitaxy at higher temperatures, leading to the formation of DyGe_x films. Thin films of Dy₂O₃ are grown on the DyGe_x film on Ge(0 0 1) substrates by molecular beam epitaxy. Streaky reflection high energy electron diffraction (RHEED) patterns reveal that epitaxial DyGe_x films grow on Ge(0 0 1) substrates with flat surfaces. X-ray diffraction (XRD) spectrum suggests the growth of an orthorhombic phase of DyGe_x films with (0 0 1) orientations. After the growth of Dy₂O₃ films, there is a change in RHEED patterns to spotty features, revealing the growth of 3D crystalline islands. XRD spectrum shows the presence of a cubic phase with (1 0 0) and (1 1 1) orientations. Atomic force microscopy image shows that the surface morphology of Dy₂O₃ films is smooth with a root mean square roughness of 10 Å.