新型结构IGBT功率模块——flowPHASE 0

现在绝大多数变频器电路的设计，都是基于印制电路板（PCB）进行的。对于小功率变频器，这样的设计可以使得变频器结构更加紧凑，实现小型化设计；对于中大功率变频器，由于现有功率模块的结构特点，通用的方法是通过铜排走线，存在的问题是成本高，寄生电感大，EMI问题严重。泰科电子（Tyco）针对这些问题，推出了基于完全PCB布线的600V，1200V IGBT功率模块，功率范围覆盖了15kW到30kW。     

生产数据准备软件CircuitCAM的特点及应用

CircuitCAM是我们在生产过程中能用到的一个非常有用的工具,用户可通过直观的方式为印制电路板（PCB）和表面贴装技术（SMT）制造中使用的100多种设备类型生成程序。该脱机软件包可将30多种CAD、Gerber及材料单数据快速转换为设备方案,而不必中断SMT生产线的运行。它不但可以生成设备程序,还可为装配员和检验员提供用于创建视像辅助资料的文档工具。文章对这个软件的一些基本功能进行了介绍,例如文件的输入输出等,使大家能在实际工作中应用,并带来方便。     

生产数据准备软件CircuitCAM的特点及应用

CircuitCAM是我们在生产过程中能用到的一个非常有用的工具,用户可通过直观的方式为印刷电路板（PCB）和表面贴装技术（SMT）制造中使用的100多种设备类型生成程序。该脱机软件包可将30多种CAD、Cerber及材料单数据快速转换为设备方案,而不必中断SMT生产线的运行。它不但可以生成设备程序,还可为装配员和检验员提供用于创建视像辅助资料的文档工具。本文对这个软件的一些基本功能进行介绍,例如文件的输入输出等,使大家能在实际工作中应用,并带来方便。     

提高倒装芯片组装速度的在线测试

倒装芯片是一种性能价格比良好的互连技术 ,要求采用富有创新的操作 ,以满足KGD的测试方法和操作工艺的需要。在基片上贴装好以前应立刻进行测试以确保能够起作用的管芯才能被装配入到倒装芯片或者说印刷电路板上面。在线测试设备是一种能够满足这些性能要求和价格要求的设备     

Multidisciplinary Placement Optimization of Heat Generating Electronic Components on a Printed Circuit Board in an Enclosure

A multidisciplinary placement optimization methodology for heat generating electronic components on a printed circuit board (PCB) subjected to forced convection in an enclosure is presented. In this methodology, thermal, electrical, and placement criteria involving junction temperature, wiring density, line length for high frequency signals, and critical component location are optimized simultaneously using the genetic algorithm. A board-level thermal performance prediction methodology based on channel flow forced convection boundary conditions is developed. The methodology consists of a combination of artificial neural networks (ANNs) and a superposition method that is able to predict PCB surface and component junction temperatures in a much shorter calculation time than the existing numerical methods. Three ANNs are used for predicting temperature rise at the PCB surface caused by a single heat source at an arbitrary location on the board, while temperature rise due to multiple heat sources is calculated using a superposition method. Compact thermal models are used for the electronic components thermal modeling. Using this optimization methodology, large calculation time reduction is achieved without losing accuracy. To demonstrate its capabilities, the present methodology is applied to a test case involving multiple heat generating component placement optimization on a PCB.     

PCB电磁兼容设计原则及其实例分析

电子设备电磁兼容要求的关键是其印制电路板（PCB）的设计,正确的PCB板布线可以经济而有效地降低其电磁干扰。文章综合PCB板电磁兼容设计相关文献,按照器件布局、地线与电源处理、时钟信号线处理等对设计经验和原则进行了较为系统的分类总结,并结合若干具体的工程实例进行了分析说明。     

Optimization of high-speed multistation SMT placement machinesusing evolutionary algorithms

Surface mount technology (SMT) is a robust methodology that has been widely used in the past decade to produce circuit boards. Analyses of the SMT assembly line have shown that the automated placement machine is often the bottleneck, regardless of the arrangement of these machines (parallel or sequential) in the assembly line. Improving and automating the placement machine is a key issue for increasing SMT production line throughput. This paper presents experimental results using genetic algorithms to optimize the feeder slot assignment problem for a high-speed parallel, multistation SMT placement machine. Four crossover operators, four selection methods, and two probability settings are used in our experiments. A penalty function is used to handle constraints. A comparison of genetic algorithms with several other optimization methods (human experts, vendor supplied software, expert systems, and local search) is presented, which supports the use of genetic algorithms for this problem     

Spacing optimization of high power LED arrays for solid state lighting

This paper provides an analytical approach to determine the optimum pitch by utilizing a thermal resistance network,under the assumption of constant luminous efficiency.This work allows an LED array design which is mounted on a printed circuit board(PCB) attached with a heat sink subject to the natural convection cooling. Being validated by finite element(FE) models,the current approach can be shown as an effective method for the determination of optimal component spacing in an LED array assembly for SSL.     

Spacing optimization of high power LED arrays for solid state lighting

This paper provides an analytical approach to determine the optimum pitch by utilizing a thermal resistance network, under the assumption of constant luminous efficiency. This work allows an LED array design which is mounted on a printed circuit board (PCB) attached with a heat sink subject to the natural convection cooling. Being validated by finite element (FE) models, the current approach can be shown as an effective method for the determination of optimal component spacing in an LED array assembly for SSL.     

EE system电子工程系统操作指南

EE system是微机上使用的电子工程系统.本文介绍该软件的主要功能和印制板布线(PCB)的操作方法.     

Integrating environmental objectives in the operational planning ofprinted circuit board assembly

This paper presents a methodology for operational control of printed circuit board (PCB) assembly systems with respect to environmental objectives for managing per-unit and per-setup waste flows. The approach builds upon the concept of unit process modeling, process chaining and evaluation of multicriteria effects first applied to product design. Three approaches are used to guide planning and control decisions for the management of hazard profiles at the facility level: product assignment, worker assignment, and a hybrid approach. The optimization models seek to balance overall waste mass and facility-level hazard given throughput constraints and demand requirements. A case example is given for scheduling six board types over four production lines in a two-shift operation     

An approach for grouping circuit cards into families to minimize assembly time on a placement machine

This paper addresses a difficult problem that often arises in printed circuit card assembly systems: how should circuit cards be grouped into families to decrease total assembly time? Traditional approaches to this problem focus on setup time, without considering the possible impacts on processing time. A new approach for selecting card families to be processed on an assembly machine is developed to minimize total assembly time through the joint consideration of setup time and processing time. The overall approach for addressing the card grouping problem involves capturing the lower level machine configuration decisions through an empirical estimator function and incorporating this function with the higher level card grouping problem. The card grouping problem is solved using a branch-and-bound algorithm supplemented by techniques to improve the solution time. An industrial case study is conducted for a turret style placement machine, a Panasonic MV150 machine. The results demonstrate the positive impact of including the lower level decisions on the total assembly time and system throughput for certain types of assembly machines. In addition, this research provides insight on other process planning problems, such as line assignment and card sequencing, by demonstrating the importance of incorporating the related lower level decision problems.     

印刷电路板温度-应力耦合场有限元分析

温度和热应力是引起印刷电路板功能失效的重要原因,针对某电子设备的PCB。对其温度-应力耦合场进行有限元分析,找出了印刷电路最大可能的失效区域;采用DOE方法对元器件结构布局进行了优化设计,使离面正负最大变形量达到最小值,应力集中得到了改善,提高了PCB的使用寿命。     

基于AVR的PCB板雕刻机的设计

为了提高PCB板制作的效率,改变传统的化学腐蚀制板工艺,使用机械仿形铣制作电路板的方法,设计了以ATMEGA16单片机为核心部件的PCB板雕刻机控制系统。其中包括PCB雕刻机的基本功能、主要硬件电路设计和软件的实现流程,并给出了相关设计电路。重点分析了雕刻机步进电机的驱动电路以及主轴电机的驱动电路,该雕刻机经实际运行,系统工作良好,可有效提高PCB板的制作效率。     

印制电路板分层改善研究

随着欧盟RoHs法令从2006年7月开始实施,印制电路板装配不得不随之无铅化,传统已使用超过50年的63Sn／37Pb焊接材料被SnAgCu（Sn96．5％／Ag3．0％／Cu0．5％）代替,熔点由原来的187℃提升到217℃,相应的焊接温度由220℃。230℃提升到240℃。260℃,印制电路板必须经历熔点以上的焊接时间多出了50多秒,印制电路板吸收热大增,印制电路板必须提高耐热性能与之配合。在过去的一年中,印制电路板分层问题一直困扰着电路板制造商。 印制板分层的机理是电路板吸热后,不同材料之间产生不同的膨胀系数而形成内应力,如果树脂与树脂,树脂与铜箔的粘接力不足以抵抗这种内应力将产生分层,所以解决分层的思路是： 1．生产流程控制尽可能保证板子有最佳的抵抗内应力的能力; 2．使用性能优越的材料减少内应力。 丈章希望通过研究,在成本和品质双重约束下,找到最佳的解决方案,用最低的成本来解决分层问题。思路是从研究分层的原因着手,通过实验设计的方法,对分层的因素从材料选择、印制电路板制造过程控制到电路板装配的整个过程,进行系统分析。 本研究项目耗费25万元的试验材料成本,历时三个多月,最终从成本和品质控制,提升公司竞争力的角度,提出解决分层的三套方案。 在将实验结果运用到A公司的实践中后,产生了良好的经济效益,每月减少客诉成本约30万元,减少成本浪费约80万元,取得超过预期效益。     

An open-source compiler and PCB synthesis tool for digital microfluidic biochips

This paper describes a publicly available, open source software framework designed to support research efforts on algorithms and control for digital microfluidic biochips (DMFBs), an emerging laboratory-on-a-chip (LoC) technology. The framework consists of two parts: a compiler, which converts an assay, specified using the BioCoder language, into a sequence of electrode activations that execute out the assay on the DMFB; and a printed circuit board (PCB) layout tool, which includes algorithms to reduce the number of control pins and PCB layers required to drive the chip from an external source. The framework also includes a suite of visualization tools for debugging, and a collection of front-end algorithms that generate mixing/dilution trees for sample preparation.     

基于电磁兼容的PCB设计

随着现代电子技术的发展以及芯片的高速化和集成化,各种电子设备系统内外的电磁环境更加复杂,因此在印制电路板的电路设计阶段考虑电磁兼容性（EMC）设计是非常重要的。这里介绍了PCB设计中的电磁兼容和产生电磁干扰的原因。从PCB的布线技术方面分析研究了改善PCBEMC性能的方法,以降低系统级和设备级在正常工作中的电磁影响。     

接触式印刷电路板检测系统的实现

设计了接触式印刷电路板检测系统,利用3个轴的步进电机驱动针头运动,对印刷电路板的电子线路的质量进行检测,并对其原理和具体的实现作了分析.通过实际应用证明,弥补了其他方案的不足,提高了检测效率.     

Evaluation on Influencing Factors of Board-Level Drop Reliability for Chip Scale Packages (Fine-Pitch Ball Grid Array)

Board-level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this study, drop test of printed circuit boards (PCBs) with a four-screw support condition was conducted for a 15 mm times 15 mm fine-pitch ball grid array (FBGA) package assembly with solder ball compositions of 36Pb-62Sn-2Ag and Sn-4Ag-0.5Cu on printed circuit board (PCB) surface finishes of organic solderability preservative, electroless nickel immersion gold, and immersion tin. Finite element modeling of the FBGA assembly was performed to study the stress-strain behavior of the solder joints during drop test. The drop test results revealed a strong influence of different intermetallic compound formation on soldered assemblies drop durability. The lead-based solder supersedes the lead-free composition regardless of the types of surface finish. Joints on organic solderability preservative were found to be strongest for each solder type. Other factors affecting drop reliability such as component location on the board and thermal cycling aging effects are reported. Finite element modeling results showed that a solder joint is more prone to failure on the PCB side, and the predicted solder joint stresses are location dependent. Predicted failure sites based on simulation results are consistent with experimental observations.