A high-speed-retry banyan switch architecture for giga-bit-rate BISDN networks

This paper proposes a high-speed ATM switch architecture for handling cell rates of several Gb/s in a broadband communication switching system or cross-connect system. The proposed switch architecture, named the high-speed-retry banyan switch, employs a bufferless banyan network between input and output buffers; a cell is repeatedly transmitted from an input buffer until it can be successfully transmitted to the desired output buffer. A simple cell-retransmission algorithm, is employed as is a ring-arbitration algorithm for cell conflict. They are suitable for FIFO type buffers and bufferless highspeed devices. Good traffic characteristics which are independent of switch size are achieved for an internal speed ratio of only four times the input line speed. A prototype system with the internal speed of 1·2 Gb/s is constructed in order to confirm the basic operation of the high-speed-retry banyan switch. The prototype system, even in its present state, could be used to realize a giga-bit-rate BISDN switching system.     

Asynchronous transfer mode (ATM) operation via satellite: Issues,challenges and resolutions

Key issues regarding the operation of the broadband integrated services digital network (BISDN) via satellite are presented herein. The specific issues, challenges, and their resolutions are detailed. In particular, the impact of error characteristics and propagation delay on the operation of BISDN via satellite is discussed. Solutions are presented for removing adverse effects and providing high-quality service to users of BISDN via satellite.     

A three-stage architecture for very large packet switches

This paper proposes a three-stage broadband packet switch architecture with more than 16,000 ports for a future central office. The switch is constructed by interconnecting many independent switch modules of small size which can be implemented using modifications of various well-studied switch fabric designs. Channel grouping is used to provide multiple paths for each input-output pair in order to decrease delay and increase throughput. We show that, for a given size, switch modules with channel grouping are simpler to realize than those without channel grouping. A datagram packet routeing approach is adopted in order to avoid table look-up that would be required by virtual-circuit routeing. Ways of preserving the sequence integrity of packets under this situation are presented. Performance analyses show that a 32,768 x 32,768 switch with acceptable performance can be constructed based on switch fabrics of no more than 128 ports.     

A fast parallel-tree switch architecture for ATM networks

In this paper we present a novel fast packet switch architecture based on Banyan interconnection networks, called parallel-tree Banyan switch fabric (PTBSF). It consists of parallel Banyans (multiple outlets) arranged in a tree topology. The packets enter at the topmost Banyan. Internal conflicts are eliminated by using a conflict-free 3 × 4 switching element which distributes conflicting cells over different Banyans. Thus, cell loss may occur only at the lowest Banyan. Increasing the number of Banyans leads to a noticeable decrease in cell loss rate. The switch can be engineered to provide arbitrarily high throughput and low cell loss rate without the use of input buffering or cell pre-processing. The performance of the switch is evaluated analytically under uniform traffic load and by simulation, under a variety of asynchronous transfer mode (ATM) traffic loads. Compared to other proposed architectures, the switch exhibited stable and excellent performance with respect to cell loss and switching delay for all studied conditions as required by ATM traffic sources. The advantages of PTBSF are modularity, regularity, self-routing, low processing overhead, high throughput and robustness, under a variety of ATM traffic conditions. © 1998 John Wiley & Sons, Ltd.     

ON IMPROVING THE DESIGN OF AN ATM SWITCH BASED ON INPUT–OUTPUT BUFFERS

We describe the development and analysis of an asynchronous transfer mode (ATM) switch architecture based on input–output buffers, a sort-Banyan network and a feedback acknowledgement (ACK) signal to be sent to the input unit. This is an input-buffer and output-buffer type of switch but with the different approach of feedback, which uses an acknowledgement feedback filter for recycling cells that lose contention at the routing network. In contrast to another design¹ which uses a merge network, a path allocation network and a concentration network at the output of the sort network to generate the acknowledgement signal, in this new proposal, the filler network has been simplified using only N filter nodes (2 × 2 switch element) and multiplexers which are placed at the feedforward of the sort network. This switch provides non-blocking, low cell loss and high throughput properties. It is designed with internal speed-up to enhance its throughput, to reduce the head of line (HOL) blocking, and to reduce the end-to-end delay.     

A high-capacity broadband packet switch architecture based on a multilink approach

Broadband packet networks based on asynchronous transfer mode (ATM) are expected to provide a wide range of services, including motion video, voice, data and image. When these networks become prevalent, some applications such as motion video and high-speed LAN interconnections will place a very large bit rate requirement on the channels. Currently, the physical layer supported by the synchronous optical network (SONET) allows the transmission of up to 2.4 Gbit/s with the OC-48 optical interface. However, it is not feasible for the electronic packet switch to route packets at this rate on a single link. In this paper we present a design of a broadband packet switch that uses multiple links in parallel to realize a high-speed channel. This implementation permits the switch to operate at the lower link rate, which can be at 150 Mbit/s, while having the ability to support a virtual circuit at a higher rate (up to 2.4 Gbit/s). The main contribution of the design is that packet sequence on a channel is still maintained even though packets are allowed to use any of the links belonging to the same channel. Besides allowing the switch to function at a slower rate than the transmission channel rate, the implementation of the multilinks benefits from statistical multiplexing gain. Analytical results show the performance advantages of multilink design with respect to delay, throughput and packet loss probability.     

Experimentation on asynchronous switching techniques for broadband ISDN

This paper deals with a proposed implementation exploiting the new asynchronous transfer mode (ATM) multiplexing and switching techniques. In particular, the basic architectural and functional choices are outlined and various aspects are examined regarding the implementation of a switching arrangement using ATM switching techniques, giving some indication about its hardware and software architecture and the foreseeable system performance.     

A multistage ATM switch with interstage buffers

Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.^1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log₂ N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log₂ N time periods. Performance analysis shows that the additional delay is small.     

Fault tolerance in Clos–Knockout multicast ATM switch

In this paper, we propose a new architecture for multicast ATM switches with fault tolerant capability based on the Clos–Knockout switch. In the new architecture, each stage has one more redundant switch module. If one switch module is faulty, the redundant module would replace the faulty one. On the other hand, under the fault‐free condition, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance. The performance analysis shows that the cell loss probability is lower than the original architecture when all modules are fault free, and the reliability of the original architecture is improved. Copyright © 2002 John Wiley & Sons, Ltd.     

Analysing the interdeparture process in an ATM multiplexer

This paper studies the interdeparture process in a mathematical model of an ATM multiplexer. The technique is based on a discrete-time queueing model of k input queues feeding one output queue, a situation commonly arising in ATM switches. The process between input queues and output queue is analysed in detail. For a service rate of one cell per time slot (s = 1) the exact solution of the interdeparture process is given based on the binomial distribution. For a service rate greater than one cell per time slot (s > 1) a solution is derived using the state probabilities of the input queues. The probability density function of the interdeparture process is then obtained by summing a combination of the multinomial joint distribution function of s random variables. If the state probabilities are referred to as the distribution of buffer contents after arrival, the formula returns exact results. © 1998 John Wiley & Sons, Ltd.     

点对多点ATM交换网络的实现与性能分析

本文中 ,我们基于Knockout交换结构 ,提出了一种能实现点到多点交换的ATM交换结构 ,并对其性能进行了分析 ,然后通过模拟证明该方法有较好的性能     

Variable rate speech coding for asynchronous transfer mode

A new speech coding and multiplexing scheme matched to the asynchronous transfer mode is described. A block coding technique that is based on a variable-rate coding algorithm that makes the most of the burstiness of voice information is employed. The main feature of the scheme is considerable bit reduction, which is attained by a fairly simple algorithm. It is demonstrated that the proposed algorithm exhibits better quality than that of a 32 kb/s ADPCM at a mean bit rate of less than 13 kb/s. The effect of statistical multiplexing is verified by means of simulation employing long conversational speech samples. Methods for constructing variable- and fixed-length frames (units of information multiplexed and transferred in the network) are proposed. The proposed coding algorithm is shown to be applicable to both variable- and fixed-length frame strategies     

Architecture design for ATM statistical multiplexers

Both high-speed packet switches and statistical multiplexers are critical elements in the ATM (asynchronous transfer mode) network. Many switch architectures have been proposed and some of them have been built, but relatively fewer statistical multiplexer architectures have been investigated to date. It has been considered that multiplexers are a special kind of switches which can be implemented with similar approaches. The main function of a statistical multiplexer, however, is to concentrate traffic from a number of input ports to a comparatively smaller number of output ports; ‘switching’ in the sense that a cell must be delivered to a specific output port is often not required. This implies that the channel grouping design principle, in which more than one path is available for each virtual circuit connection, can be applied in the multiplexer. We show that this technique reduces the required buffer memory and increases the system performance significantly. The performances of three general approaches for implementing an ATM statistical multiplexer are studied through simulations with various bursty traffic assumptions. Based on the best performing approach (sharing output channels and buffers), we propose two architecture designs to implement a scalable statistical multiplexer that is modularly decomposed into many smaller multiplexers by using a novel grouping network.     

An efficient method for computing cell loss probability for heterogeneous bursty traffic in ATM networks

In this paper, we present an approximation for the probability of cell loss of heterogeneous bursty traffic in broadband integrated packet networks based on the asynchronous transfer mode. The sources considered here alternate between active and silent periods and are characterized by their peak and average transmission rates. The cell loss probability is obtained by considering only the number of active sources at a given time and computing the amount of traffic that exceeds the link capacity. Since the amount of buffered excess traffic is not considered in this computation, this approximation is actually an upper bound of the cell loss probability. The numerical efficiency of this bound enables it to be used as a measure based on which robust and simple resource allocation strategies can be developed for bursty sources. Comparison of this bound with the simulation results has shown that the bound is close to the actual loss probabilities especially for large burst lengths and high utilizations.     

基于色散的ATM自由空间光交换结构

根据波导型光交换的一些弱点，提出了一类克服以上缺点的基于色散异步转移模式（ＡＴＭ）的自由空间光交换结构，并对该结构进行了一些讨论。     

Networking a la mode [asynchronous transfer mode]

The asynchronous transfer mode (ATM) was developed at the behest of the telecommunications industry, but is being deployed principally within private data networks. In this paper, the author explains this apparent paradox     

ATM网信息元选择性丢失的分析

在ＡＴＭ网里信息元选择性丢（ＳＣＤ）是一个十分重要的问题。本文提出了一种两优先级ＳＣＤ方法，并对这种方法的性能在信息元离散时间到达的条件下进行了分析，克服了泊松到达假定的不足。通过引进π算子给出了一种能够加快收敛速度的计算信息元丢失概率的迭代算法。证明了ＳＣＤ方法在ＡＴＭ网中的有效性。     

A connection control strategy for bursty sources in broadband packet networks

This paper proposes an admission strategy for connection-oriented services at the access node of a broadband integrated packet network based on asynchronous transfer mode. Based on an estimate of the probability of cell loss and in the absence of buffering, we determine the number of sources from different classes of bursty traffic which can be accepted. The parameters which are used to describe the traffic sources are average bit rate and peak bit rate. We will evaluate the cell loss estimate for homogeneous and heterogeneous cases. Furthermore, we will examine the variation of this estimate as the average to peak ratio changes. The estimate is an upper bound for the probability of cell loss. Based on this upper bound simple and robust allocation of resources to bursty sources can be developed. The proposed strategy can be implemented using simple computations or via a look-up table to determine admission or denial of an incoming call and therefore allocating the required capacity. The procedure results in efficient use of the bandwidth, ensuring the desired service quality for connection-oriented services and results in proactive control of network congestion.