新型超宽带探地雷达数字采样接收机设计

基于探地雷达应用,结合等效时间采样技术和实时采样技术的优点,提出了一种新的超宽带等效数字采样技术。该采样技术不需要采用集成模数转换(A/D),而是通过对模拟信号进行1比特并行时间交替采样和均匀量化来实现模数转换的功能。基于该技术思想,利用一片现场可编程门阵列(FPGA)研制出具有等效4.096GHz采样率、7位精度模数转换功能的超带宽探地雷达数字采样接收机。电路结构紧凑,功耗低于1.5W.实测结果表明:该接收机的模拟带宽达500MHz,具有很低的量化噪声,能很好的重构输入信号。同时,该接收机具有很好的性能,能满足超宽带探地雷达的要求。     

超宽带信号监测处理中关键技术研究

以瞬时带宽超过1 CHz的超宽带信号监测处理为应用背景,利用高性能FPGA和超高速ADC实现了超高速数据采集、海量数字存储的技术方案.基于此方案的终端处理系统采用软件无线电技术架构,对1 GHz超宽带信号具有实时监测处理功能、实时引导干扰能力;实验测得系统采样速率600 Msps时系统信纳比达到44dB,有效位数为7.1b,达到了较好的实验效果.     

一种超宽带等效采样接收机的设计与实现

脉冲超宽带雷达回波信号由于带宽大而难以直接采样,通常采用等效时间采样方法来进行模数转换。传统的等效采样接收机大都是基于改变ADC采样时钟的时延来实现等效采样,采样时钟对触发信号会产生亚稳态时序,不可避免地会出现数据误对齐,必须添加辅助的在线或离线校正设计。针对这一问题,设计了一种基于FPGA内置延迟线的超宽带等效采样接收机,FPGA产生延时可调的发射触发信号去控制波形产生系统,基于高速采样保持器和ADC完成回波接收,实现了超宽带射频信号的等效采样,而无数据误对齐问题。接收机的等效采样速率为12.8GS/s,-3dB采样带宽为6.4GHz,满足脉冲超宽带雷达的应用需求。     

基于超宽带采样保持器的数字接收机设计

直接射频采样技术是数字接收机的发展新趋势。由于 ADC 器件的水平限制,直接射频采样技术在接收机中的应用受到很大的限制。采用 SHA（采样保持器）＋ADC 的系统结构,设计了一种支持超宽带信号输入的数字接收机,实现了射频信号的直接采样。简述了采样保持器的工作原理,介绍了直接射频采样数字接收机的系统组成,详细介绍了数据采集子板的设计。综合 FPGA 分析工具 CHIPSCOPE 与MATLAB 软件,对数字接收机进行了测试和指标分析。结果表明,该数字接收机在采样保持器带宽范围内,可以满足常规指标要求,简化了系统设计,降低了成本,具有一定的应用价值。     

采用射频直采技术的超宽带软件无线电平台

针对现代无线电系统对超宽带、可重构、多功能等需求日益增长的问题,基于射频直接采样技术,构建了一套符合PXI(PCI extensions for Instrumentation)标准的通用化超宽带软件无线电平台,硬件上以数模转换芯片AD9173和模数转换芯片ADC083000为核心,直接采样率高达3 Gsample/s;采用20 nm工艺制程的UltraScale Kintex FPGA,以IP(Intellectual Property)化开发理念设计FPGA固件,实现用户可编程。该平台能够满足0.1~1.4 GHz超宽带软件无线电应用需求,瞬时带宽高达1.3 GHz。     

IR-UWB数字相干接收机的硬件电路设计

在超宽带信号的接收中,相干接收比非相干接收拥有更高的分辨率,能充分发挥超宽带信号定位精度高等优点.相干接收机对UWB信号进行高速采样后再处理,采样的速度和精度是限制UWB相干接收机测距精度的主要因素.本文设计并实现了IR-UWB的数字相干接收机,接收机采用高速采样芯片ADC08D1000对脉冲超宽带（IR-UWB）信号进行双通道交织采样,然后使用FPGA对采样数据进行降速处理.测试结果证明,本文设计的接收机能准确捕获到脉宽为1 ns的UWB信号.     

计算技术与计算机

0017047多功能环保显示系统[刊]/吴元锋//电子机械工程.—2000,(2).—26～28,37(K)0017048驱动器嵌入式技术分析[刊]/季军杰//计算机工程.—2000,26(6).—80～82(K)从出错处理、接口自动化、缓冲区管理及节能等方面对驱动器中嵌入式控制器智能技术进行了分析。0017049基于数字处理技术的 ADC 动态测试及分析[刊]/李迅波//仪器仪表学报.—2000,21(3).—293～296(E)本文分析了 ADC 频域测试中采样数据的频谱组成,给出了高准确度 ADC 频域测试的条件。采用数字处理技术对高速 ADC 的动态特性进行了测试和分析,其结果对 ADC 及其采样电路的设计具有指导意义。参5     

宽带数字预失真硬件平台设计与实现

针对第3代移动网络基站射频功率放大器的线性化需求的不断提高和立足于未来第4代移动通信系统基站,设计并实现了一款以FPGA为核心的宽带数字预失真硬件平台。首先,对整体硬件框架进行了阐述并着重分析了LTM9003的带通采样定理和AD9788的数字单边带调制;其次,根据2-D(ADC)和ADC多次采样技术,提出了超宽带矢量信号测试的系统结构和原理实现;最后,对整机进行了ADC和DAC链路的测试,测试结果表明其性能基本达到了数字预失真的需求。     

高性能A/D转换器校准技术研究进展

A/D转换器(ADC)的校准技术是提高高性能ADC转换精度的必要手段,它分为模拟校准技术和数字校准技术。数字校准技术较之模拟校准技术更为有效和更具灵活性。数字校准技术是在数字域进行错误代码计算,减轻了对模拟电路的精度要求。在主流制造工艺小尺寸化的趋势之下,许多创新的校准技术得到发展,并广泛应用于包括射频直接采样ADC在内的高速高精度ADC中。本文在分析最新的高速高精度ADC中采用的主要校准技术的基础上,重点研究了几种高采样率高精度ADC所采用的校准技术,侧重分析了数字校准技术。     

基于高速ADC和FPGA的IR-UWB相干接收机设计

为了探索超宽带(UWB)技术的空间应用,设计了一款脉冲无线超宽带(IR-UWB)的全数字化相干接收机。本系统利用高速采样芯片ADC08D1000对IR-UWB信号进行双通道交织采样,接下来利用Xilinx FPGA对采样数据进行降速处理。按照二分搜索、相干捕获、脉冲跟踪的方案进行接收系统设计,并对该接收机进行了实际测试。最终实现了1 ns脉宽的IR-UWB信号的正确接收和1 Mb/s码速率的OOK编码通信。     

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

Analysis and Implementation of a Time-Interleaved ADC Array for a Software-Defined UWB Receiver

A software-defined radio (SDR) for ultrawideband (UWB) communication systems places several stringent requirements on the analog-to-digital converter (ADC). One alternative to using a single ADC is to sample the received signal with an array of lower speed ADCs that were driven by interleaved sampling clocks; however, mismatches among the ADCs will result in signal distortion. This paper makes three important contributions to overcoming this problem: 1) analytical quantification of the impact of ADC gain, offset, and timing mismatches on the performance of a time-interleaved sampling ADC array for UWB signals; 2) demonstration of the efficacy of using a pilot-based matched-filter architecture to mitigate the impact of timing mismatches in the presence of multipath; and 3) implementation of an 8-ADC time-interleaved UWB SDR testbed that operates at an effective sampling frequency of 6.4 GHz. In addition, our findings allow for the design specification of the number of pilots required to obtain a desired system performance. The simulation and measured performance results from this paper demonstrate that ADC mismatches can be controlled to within plusmn10%, yielding acceptable levels of distortion and bit-error-rate (BER) performance on the UWB SDR testbed. Both analytical and simulation results also demonstrate the efficacy of a pilot-based matched filter in mitigating the impact of timing mismatch errors, even in the presence of multipath.     

Ultra-wideband analog-to-digital conversion via signal expansion

We consider analog to digital (A/D) conversion, based on the quantization of coefficients obtained via the projection of a continuous time signal over a set of basis functions. The framework presented here for A/D conversion is motivated by the sampling of an input signal in domains which may lead to significantly less demanding A/D conversion characteristics, i.e., lower sampling rates and lower bit resolution requirements. We show that the proposed system efficiently parallelizes the analog to digital converter (ADC), which lowers the sampling rate requirements by increasing the number of basis functions on which the continuous time signal is projected, leading to a tradeoff between sampling rate reduction and system complexity. Additionally, the A/D conversion resolution requirements can be reduced by optimally assigning the available number of bits according to the variance distribution of the coefficients obtained from the signal projection over the new A/D conversion domain. In particular, we study A/D conversion in the frequency domain, where samples of the continuous signal spectrum are taken such that no time aliasing occurs in the discrete time version of the signal. We show that the frequency domain ADC overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. The proposed A/D conversion method is compared with conventional ADCs based on pulse code modulation (PCM). Fundamental figures of merit in A/D conversion and system tradeoffs are discussed for the proposed ADC. The signal-to-noise and distortion ratios of the frequency domain ADC are presented, which quantify the impact of the most critical impairments of the proposed ADC technique. We also consider application to communications receivers, and provide a design example of a multi-carrier UWB receiver.     

一种新的数字阵列雷达接收机技术

高速ADC和先进DSP器件的进展使数字波束形成智能天线的实现成为现实。在传统的M单元天线阵系统中,每一单元都有各自的接收通道和ADC,设备量大。文中提出了一种适合于多通道数字阵列雷达接收系统的新型数字接收机结构,其主要思想是基于多个不同信号的带通采样原理实现数字阵列雷达接收机,新接收机结构使IF接收通道和基带采样ADC显著减少,功耗大大降低。阐述了数字阵列接收的数据模型和工作原理,分析了多信号带通采样信号频率和采样率的关系,给出了采样率选取的约束条件。新接收机在降低设备量的同时,还减小了接收系统通道间幅一相不一致性失真。     

一种应用于流水线ADC的自适应后台校正技术

流水线模数转换器(Pipeline ADC)是一种应用广泛的模数转换器结构,可以同时实现高速和高精度性能。然而电路的非理想性严重制约着流水线ADC的性能。提出了一种自适应数字技术,通过使用低速但准确的ADC作为基准,与待校正的流水线ADC并联,并将两者的数字输出的差值送入数字自适应滤波器中进行处理,使流水线ADC的输出不断逼近低速但准确的ADC输出,从而达到数字校正的目的。仿真结果表明,这种方法可以有效去除包括电容失配、有限运放增益、运放失调在内的误差。     

A channelized digital receiver design for UWB systems in a multi-path indoor environment

Due to the very wide bandwidth of UWB system, it is hard if not impossible to design high speed and high resolution ADCs with today’s technology. This problem can be solved if the received UWB signal is split into a number of subbands by power splitters, analog low-pass filters, mixers and digital filters. By doing this, each of subbands can be sampled at a fraction of effective sampling frequency. In this paper, we present a simpler channelized receiver architecture for UWB systems than previously published work. Moreover, we present a new, though more complex, channelized receiver design for UWB systems in a multipath propagation environment. We also show through simulation that this new receiver achieves very good BER performance.     

一种基于FPGA的超宽带雷达数字接收机

脉冲超宽带雷达回波信号由于带宽大而难以直接采样,文中设计并实现了一种基于FPGA的数字式脉冲超宽带雷达接收机。该接收机利用FPGA内嵌锁相环产生特定频率的时钟,驱动四路10 bit ADC器件,根据回波信号在一段时间内呈准静态及周期性的特点,实现了四通道时域伪随机等效采样。仿真及测试结果表明,该数字式脉冲超宽带雷达接收机等效采样速率可达10 GS/s,可有效接收雷达回波信号,满足脉冲超宽带雷达的应用需求。     

光学模数转换器的原理及发展

模数转换器（ADC）是许多信息处理系统的关键组成部分。由于电子模数转换器的缓慢进展，使其成为模拟信号和数字处理系统之间的瓶颈因素，这促使人们对采用光学技术提高模数转换器的采样速率和精度产生了兴趣。本文详细阐述了光学模数转换器（OADC）的原理及发展，对其应用及未来的发展进行了探讨。