H.264/AVC中二进制算术编码的分析与研究

算术编码是一种高效的熵编码方法，已经广泛应用于图像和视频编码中。文中简述了算术编码的基本原理，介绍了可行的算术编码算法，详细分析了H．264／AVC的CABAC中采用的自适应二进制算术编码的算法并对其性能进行了测试。     

H．264／AVC中二进制算术编码的研究

基于上下文的二进制算术编码（CABAC）是H．264／AVC中采用的一种高效的熵编码方法。本文简述算术编码的基本原理和CABAC的步骤．详细分析了二进制算术编码的过程。     

H.264中二进制化编码器的FPGA实现

H.264是最有前景的视频压缩标准,熵编码是其中重要的一环,但算法比较复杂,执行速度不高.对熵编码中的二进制化器进行改进,提出一种基于流水线的FPGA结构.对软件流程进行部分改进以提高速度,采用流水线及并行处理技术设计整个电路.在Spartan3 FPGA上实现该电路,编码速度达1bit/cycle,最高时钟频率可达100 MHz.     

高清H.264CABAC解码器的优化设计

针对能够在FPGA 上实现实时解码H.264/AVC 高清晰视频序列码流的目标,本文提出了一种基于上下文的自适应二进制算术编码（CABAC）解码器的硬件设计结构,旨在解决解码过程中并行程度低,以及存储资源消耗大的问题.该设计对解码流程中的存储结构和关键路径进行优化,并采用了硬件加速,从而显著地提高了CABAC 的解码效率并充分利用了存储空间.测试结果表明,该方案能够满足H.264/AVC 高级档次高清视频序列实时解码系统的要求.     

基于上下文的自适应二进制算术编码的硬件实现

文章提出了一种适用H.264标准的自适应算术编码器的VLSI实现方案,它对算术编码的结构做了改进,用查表代替了乘法操作,并采用流水线结构实现,获得了较高的吞吐速率.在采用Verilog语言对编码模块进行描述后,用ALTEAR公司的现场可编程门阵列（FPGA）进行仿真验证.实验表明,这种流水线结构的算术编码器能够获得较高的编码速度.     

H.264/AVC中基于上下文的自适应二进制算术编码

基于上下文自适应二进制算术编码(CABAC)H．264／AVC采用的高效熵编码方法之一,它由二进制化、上下文建模、算术编码三个步骤构成。详细阐述了CABAC的整个编码过程,并对它与VLC／CAVLC在编码性能上作了比较。     

H．264中二进制化编码器的FPGA实现

H．264是最有前景的视频压缩标准,熵编码是其中重要的一环,但算法比较复杂,执行速度不高。对熵编码中的二进制化器进行改进,提出一种基于流水线的FPGA结构。对软件流程进行部分改进以提高速度,采用流水线及并行处理技术设计整个电路。在Spartan3FPGA上实现该电路,编码速度达1bit／cycle,最高时钟频率可达100MHz。     

自适应算术码及其解码器的硬件实现

H.264／AVC是由联合视频小组（JVT）在2003年5月提出的最新视频压缩标准。基于上下文自适应二进制算术编码（CABAC）是H．264／AVC提高编码效率最重要的工具之一。本文提出了一种CABAC解码器体系结构。极大地提高系统性能和解码速度，可以实现对高清码流的解码。     

基于HEVC的CABAC二进制算术编码器的FPGA实现

本文基于H.265/HEVC视频编码标准,实现了CABAC编码中二进制算术编码器常规编码模式下的一种硬件流水线结构,根据算法特性设计并优化了编码器的硬件架构,将概率状态数据储存在SRAM中,并使用查找表优化概率估计更新运算;对编码数据进行打包处理,简化概率估计更新带来的计算,以优化视频数据流编码速度;二进制算术编码采用多级流水线结构,支持四路并行编码。仿真结果表明,本文的硬件CABAC二进制算术编码器平均每时钟周期可以完成4个bin的编码,符合较高帧率的1080p视频实时编码要求。     

AVS＋熵编码关键技术比较研究

AVS＋是我国2012年颁布的新一代视频编码标准。AVS＋中采用了两种熵编码方法,一种是基于上下文的自适应变长编码CAVLC;另一种为基于上下文的自适应二进制算术编码CABAC。已经有人对H.264标准比较了两种编码体制的优劣,本文针对AVS＋编码应用,简述分析二者算法原理,对照比较其特点,通过测试表明CABAC耗时稍长,但是比CAVLC更加高效。     

高速Berlekamp-Massey算法结构及电路实现

介绍了两种用于二进制BCH解码器的高速Berlekamp—Massey算法实现方案。在加入寄存器以减少关键路径的延时从而提高电路速度的基础上，一种方法是采用有限域乘法器复用的方法降低电路的复杂度；另一种方法则通过对有限域乘法器进行流水线设计，进一步提高电路的工作速度，实现超高速应用。设计中充分利用了二进制BCH码中Berlekamp—Massey算法迭代计算时修正值间隔为零的性质，用超前计算的方法减少了运算周期的增加。提出的方案可用于设计高速光通信系统的信号编解码芯片。     

The Generation of High-Speed Binary Sequences from Interleaved Low-Speed Sequences

This paper deals with the theory of generating high-speed binary sequences by interleaving two lower speed sequences which are displaced by half a bit period with respect to each other. The interleaving can be carried out by using a high-speed switch which is clocked at twice the clock rate of the lower speed sequences or by modulo 2 addition of the displaced sequences. Starting from any binary sequence, we give a general theory for the derivation of the binary sequences which are to be interleaved to produce any required high-speed sequence. We also deal with the particular case ofm-sequences.     

基于RRAM双交叉阵列结构的三值存内逻辑电路设计

在RRAM交叉阵列结构中实现逻辑运算可以较好地解决传统冯诺依曼架构中的存储墙问题.三值逻辑相比于传统的二值逻辑,具有更少的逻辑操作数目和更快的运算速度.文中提出了一种基于RRAM双交叉阵列结构的三值存内逻辑电路设计,其中三值逻辑电路的输入与输出均通过多值RRAM的阻值表示.该结构支持两种三值逻辑门和一种二值逻辑门以提升...     

Windows CE下GPS导航设备的启动速度的优化

基于Windows CE的GPS导航设备,由于系统的采用的FAT文件系统自身的缺陷,导致启动速度缓慢.经过深入分析Nand Flash驱动程序,FAT文件系统以及导航地图数据的特点,提出了一种优化导航设备启动速度的方法,该方法分为两个步骤,第一步将地图文件转换为可下载的bin文件格式; 第二步通过EBOOT下载该bin文件.目前该方法已经应用到导航设备中,实测表明,该方法可以显著的提高导航设备的启动速度.     

On the use of Reed-Solomon codes in improving digital FMtransmission performance in Rayleigh fading

Reed Solomon codes with interleaving are used in a binary FM transmission affected by Rayleigh fading as encountered in land mobile radio. A new decoding algorithm is proposed which can be implemented in simple hardware. The error performance of the binary FM system with the RS code with one and two degrees of interleaving is measured. A significant reduction of error rate floor as a function of fading speed is noted and discussed     

Better OPM/L Text Compression

An OPM/L data compression scheme suggested by Ziv and Lempel, LZ77, is applied to text compression. A slightly modified version suggested by Storer and Szymanski, LZSS, is found to achieve compression ratios as good as most existing schemes for a wide range of texts. LZSS decoding is very fast, and comparatively little memory is required for encoding and decoding. Although the time complexity of LZ77 and LZSS encoding isO(M)for a text ofMcharacters, straightforward implementations are very slow. The time consuming step of these algorithms is a search for the longest string match. Here a binary search tree is used to find the longest string match, and experiments show that this results in a dramatic increase in encoding speed. The binary tree algorithm can be used to speed up other OPM/L schemes, and other applications where a longest string match is required. Although the LZSS scheme imposes a limit on the length of a match, the binary tree algorithm will work without any limit.     

An improved SMM algorithm

A new fast algorithm to compute modular exponentiation for very large integers is proposed in this paper, which is an improvement of the fast RSA algorithm based on Symmetry of Modular Multiplication(SMM). The SMM algorithm obtains the speed improvement by conditional substitution on every basic operation to decrease the absolute value of product and the operation numbers of modular reductions. The proposed algorithm can get faster operation speed by decreasing the numbers of basic operations. Compared to conventional binary representation, a speed improvement of approximately 47.5% would be expected using the proposed algorithm.     

基于SD数表示的求和算法

二进制加法器已广泛应用于数字系统，但传统的二进制数表示求和过程中产生的进位限制了运算速度。文中提出了一种以2为基数的SD（Singed-Digit)数表示的求和计算方法，并在此基础上应用可编程逻辑器件设计实现了SD加法器，简化了求和运算过程。实验证明，通过这种算法可得到高速加法器，以提高运算速度。     

BPC – A binary priority countdown protocol

In modern wireless ad hoc networks, with a high speed PHY, every collision means a significant loss of useful bandwidth. In the last few years different binary contention protocols have been introduced to address this problem. In this work we propose a novel binary contention protocol called binary priority countdown (BPC) protocol, whose goal is to reduce collisions as well as contention time. BPC uses a new priority countdown mechanism which exploits the efficiency of binary countdown, but the priority countdown process is not constrained to a single binary countdown round. This way, the priority space is not defined by the length of binary countdown round, like in other binary countdown protocols proposed in the literature, and arbitrary medium access priorities can be decremented through multiple binary countdown rounds if necessary. The ability of a new priority countdown mechanism to count down any priority number without changing the length of a binary countdown round, allows independent management of priority space. This “independence” of priority space introduces new optimization and adaptation possibilities. Collision memory effect is recognized and described. BPC protocol reveals connection between unary, binary and digit contention protocols. All three groups of protocols can now be seen as members of the same class of contention algorithms. Preliminary simulation results are shown.     

Pipeline array for square-root extraction

Pipelining an arithmetic process is a well known technique for improving the computation speed of the arithmetic algorithm. In the letter is proposed a pipeline version of the array for the extraction of square roots of binary numbers. It is shown that a significant speed improvement (on a throughout basis) can result by this modification of the conventional logic arrays.