信号的低比特位数表示：一种新颖低比特位数的∑-△调制器

摘要：通过设计一种新的噪声整形滤波器，本文提出了一种新颖的∑-△调制器结构，可用于实现用较低比特位数的数字信号表示较高比特位数的输入信号．该调制器与传统的∑-△调制器相比，其输出数字信号比特位数(或动态范围)降低了许多．理论推导分析和仿真对比的结果表明，在量化噪声整形和噪声频谱上，该调制器的各项性能有了很大的提高，而且证明了这类调制器是稳定的．     

信号的低比特位数表示:一种新颖低比特位数的Σ-Δ调制器

通过设计一种新的噪声整形滤波器,本文提出了一种新颖的Σ-Δ调制器结构,可用于实现用较低比特位数的数字信号表示较高比特位数的输入信号.该调制器与传统的Σ-Δ调制器相比,其输出数字信号比特位数(或动态范围)降低了许多.理论推导分析和仿真对比的结果表明,在量化噪声整形和噪声频谱上,该调制器的各项性能有了很大的提高,而且证明了这类调制器是稳定的.     

基于高阶单比特∑△调制器的频率综合器

本文介绍了高阶单比特∑△调制器在小数分频频率综合器中的应用。普通小数分频频率综合器容易产生很大的杂散频率，采用∑△调制器可以有效消除杂散频率降低相位噪声。由于多比特MASH结构的非线性，这里采用单比特高阶∑△调制器（CIFB），最后提出实现电路。     

用于音频过采样D/A转换器的∑-△调制器设计研究

文章针对采样频率为44.1kHz的16位数字音频信号，采用CookBook方法，研究设计了用于过采样率为64倍的音频数模转换器的五阶3比特输出sigma-deha（∑-△）调制器。该调制器通带内信噪比（SNR）的matlab仿真实验结果达到了120dB以上，能够很好的抑制通带内噪声。该调制器设计结构采用前反馈和负反馈分支的∑△型．大大降低了电路的复杂性，使硬件实现十分方便，具有重要的应用价值。     

调制器、解调器

Y98-61460-138 9915228用0.4μm 高电子迁移率晶体管技术设计高抽样率持续∑△调制器模拟元件的研究=Design of the analogcomponents for high sampling rate continuous ∑△ modu-lation in 0.4μm HEMT technology[会,英]/Olmos.A.& Miyashita.T.//1998 IEEE 2nd International CaracasConference on Devices.Circuits and Systems.—138～141(YG)本文提出了一种利用0.4μm InGaP/InGaAs 高电子迁移率晶体管技术设计的高抽样比∑△调制器的关键元件.该二级持续时间∑△调制器电路具有与其它电路完全不同的结构,包括一对高线性度 V-I 转换器,高速运算放大器.高速1比特数模转换单元,和一种新     

调制与解调技术、调制解调器

Y2001-62724-21 0115074多速率-多比特∑△调制器=Multirate-multibit Sigma-Delta modulators[会,英]/Colodro,F.& Torralba,A.//2000 IEEE International Symposium on Circuitsand Systems,V01.2.一21～24(HC)本文提出实现∑△调制器的多速率特性,称为多速率多比特(MM)∑△调制器的特性与工作于一次积分器时钟速率的常用多比特∑△调制器一样,但是通过增加二次积分器的时钟速率代替正向路径的 ADC,文中给出理论和模拟结果。参10     

低电压∑-△调制器关键技术及设计实例

介绍了低电压开关电容∑-△调制器的实现难点及解决方案,并设计了一种1V工作电压的∑-△调制器。在0．18μm CMOS工艺下,该∑-△调制器采样频率为6．25MHz,过采样比为156,信号带宽为20kHz;在输入信号为5．149kHz时,仿真得到∑-△调制器的峰值信号噪声失真比达到102dB,功耗约为5mW。     

14-b 400-ksps 2.5-mW连续时间∑-Δ调制器

连续时间∑-△调制器较之传统的开关电容∑-△调制器具有更低的功耗、更小的面积,以及集成抗混叠滤波器等诸多优势.设计了一种应用于低中频GSM接收机的4阶单环单比特结构的连续时间∑-△调制器.在调制器中,采用了开关电容D/A转换器,以降低时钟抖动对性能的影响.仿真结果显示,在1.8 V工作电压、200 kHz信号带宽、0.18 μm CMOS工艺条件下,采样频率21 MHz,动态范围(DR)超过90 dB,功耗不超过2.5 mW.     

16位数字二阶∑-△调制器的分析与设计

文章阐述了∑-△调制器的基本工作原理,构建了二阶∑-△调制器的基本结构,提出了一种用Verilog HDL语言描述二阶∑-△调制器的实现方法,其中采用了简单的移位方法来描述调制器的四个增益系数,以实现乘法操作,进而减小了芯片的面积。在此基础上,运用MATLAB系统工具建立了二阶∑-△调制器系统的模型,并完成了系统仿真验证。在电路级完成了它的Verilog语言描述,同时运用modelsim仿真工具对电路进行仿真验证,对数据进行FFT分析,最终证明了MATLAB系统模型和Verilog代码的一致性。     

应用于无线传感网络 SOC的低功耗∑△调制器

提出了一种应用于无线传感网络 SOC过采样率（OSR）为128的单环三阶单比特量化∑△调制器．通过采用新型前馈结构,降低了系统对运算放大器性能的要求;通过采用新颖的两级Class A/AB运算放大器实现积分器电路,有效降低了电路的功耗;为了进一步降低电路功耗,对调制器中的第二级、第三级运放进行了缩放．该调制器采用华虹0．18μm CMOS工艺,输入信号带宽为8 kHz ,工作电压1．8V ．后仿真结果表明：在输入信号频率为5 kHz、采样时钟为2．048 M Hz时,调制器的信噪比（SNR）达到96dB ,整个调制器的功耗仅为180μW ,芯片总面积为0．51 mm2．     

A 1.2-MHz 10-bit Continuous-Time Sigma–Delta ADC Using a Time Encoding Quantizer

This paper shows the operating principle and experimental results of a new continuous-time sigma–delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-${rm mu}{hbox{m}}$ CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.      

A Novel Architecture of Delta-Sigma Modulator Enabling All-Digital Multiband Multistandard RF Transmitters Design

This paper proposes a new architecture of delta-sigma (DS) modulator suitable for RF digital transmitter design. This novel architecture considerably reduces the speed requirements of the digital signal processing block. The novelty lies in the implementation of a specific fully digital up-conversion in combination with a low-pass DS modulator to produce high-frequency digital-like signals, which can be used to drive highly efficient switching-mode power amplifiers. The proposed architecture is suitable for reconfigurable all-digital, multistandard and multiband wireless transmitters. The novel transmitter architecture has been validated using simulation and implemented on a field-programmable gate array development board for two different signals, code division multiple access and orthogonal frequency division multiplex.      

多比特增量-总和调制器中的降噪环路

在单级多比特增量-总和调制器中,量化器的规模是与其比特数成指数增长的,当比特数增加时,量化器会很快变得难以实现.本文提出了一种新结构:降噪环路(Noise-Reducing Loop),能够利用较少比特的量化器获得较多比特量化器的效果,在获得高信噪比的同时,大大地减小了电路规模.在此基础上应用动态量化(Dynamic Quantization)算法,可以使调制器在很宽的工作范围内具有较高的性能.     

Time-based all-digital sigma–delta modulators for nanometer low voltage CMOS data converters

A phase-based delta?Csigma (????) analog-to-digital converter (ADC) is proposed and the idea is demonstrated using two architectures. The first architecture adopts a delay-locked-loop (DLL) mechanism. It is realized by a modification of a DLL using a voltage-controlled delay line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed ???? ADC achieved 50.5?dB SNDR or 8.09?bits resolution for a 10?MHz signal bandwidth. The second architecture adopts a combination of voltage-controlled and digitally-controlled delay lines (VCDL?CDCDL) as the phase-domain counterparts of an ADC?CDAC in a traditional delta?Csigma modulator. Simulation results of the new modulator achieve a 57.8?dB SNR, or a 9.28 bit over a 10?MHz bandwidth.     

基于ΣΔ调制的Tetra基带前端设计

抗混叠滤波和模数转换器性能严重影响到后续接收机的数字处理。高分辨率A/D转换虽然可改善信号/量化噪声比,但也要求抗混叠滤波器有更低阻带衰减,致使其实现复杂、成本增加。在Tetra系统基带设计中,采用过采样ΣΔ调制可平衡高比特A/D转换与简单抗混叠滤波两者矛盾的要求。在分析ΣΔ调制的噪声整形基础上,针对Tetra系统要求,完成过采样3阶ΣΔ调制器及1/16降速抽取滤波器设计,MATLAB仿真验证了设计的正确和有效性,给出了相关的设计结果。     

Superconducting sigma-delta analog-to-digital converters

The sigma-delta architecture is the method of choice for designers and manufacturers of analog-to-digital converters (ADCs) for high dynamic range applications. This architecture uses oversampling and precise feedback to generate a shaped spectral distribution of the quantization noise. Subsequent digital filtering suppresses out of band quantization noise, yielding a large signal to in-band noise ratio. This permits the use of quantizers with only a few bits of resolution, most applications use single-bit quantizers. A unique advantage of superconducting electronics is the availability of the flux quantum which can be used to provide quantum mechanically accurate feedback at GHz rates. Josephson digital technology extends the realm of sigma-delta ADCs from MHz sampling rates to GHz sampling rates, from kHz signal bandwidths to MHz signal bandwidths, with comparable or better dynamic range when compared to semiconductor implementations. This paper presents circuits for Josephson sigma-delta ADCs, including single-loop, and double-loop modulators, circuits for quantized feedback, and digital data processing. Experimental results of a double-loop modulator sampling at 1.28 GHz are reported.     

一种采用并行光强度调制器的模数转换方法

提出了一种采用并行光强度调制器实现移相光量化的方法。利用对光强度的衰减实现量化曲线的相移,解决了现有移相光量化方案中相位调制器对环境、温度较为敏感,量化曲线相移控制精度以及脉冲走离的问题。采用两个铌酸锂强度调制器并行连接,每个光耦合器分成4个通道,每个通道中插入光衰减器,通过调节光衰减器实现通道间调制曲线的相移,构成8通道4 bits的光量化器。实验中对10 GHz的正弦信号进行了光量化测试,量化结果的有效比特数(ENOB)为3.7 bits,仅低于理想分辨率0.3 bits。实验结果表明该方案可行,与一般移相光量化方案相比,具有较高的有效比特数。     

Hybrid continuous-time/discrete-time cascade σδ modulator with adaptive inter-stage resonation

A novel architecture of a hybrid continuous-time/discrete-time cascade ΣΔ modulator that takes advantage of both circuit techniques, by including implicit anti-aliasing filtering and reduced sampling requirements, while presenting high robustness to circuit non-idealities, is presented. These circuital features are combined with programmable resonation to optimally distribute the zeros of the noise transfer function. In addition, the unity signal transfer function is implemented in all the modulator stages in order to reduce the integrator?s output swing. All these characteristics make the proposed architecture well suited to the implementation of reconfigurable A/D conversion in future generations of wireless telecom systems.     

Force-balance interface circuit based on floating MOSFET capacitors for micro-machined capacitive accelerometers

The feasibility of a force-balance interface based on a second-order delta-sigma (/spl Delta//spl Sigma/) modulator for capacitive sensors has been analyzed in order to delimit the requirements to assure system stability for a given set of constraints related to the sensor-modulator system. A /spl Delta//spl Sigma/ modulator based on a switched-capacitor architecture with floating MOSFET capacitors has been implemented using a 0.7-/spl mu/m CMOS process. Nonlinear effects related to voltage dependence of the floating MOSFET capacitors have been avoided using a modulator architecture based on charge integrators. The behavior of the new proposed modulator has been measured experimentally and compared with an equivalent interface made with lineal capacitors. Similar results were obtained from both systems. In both circuits, the modulator resolution was better than 14 bits at a sample frequency of 250 kHz, and oversampling ratio of 256.