Radio transceivers for wireless personal area networks using IEEE802.15.4 - [integrated circuits for communications]

This article describes the design considerations for low-power short-range radio transceivers with a focus on the 2.4 GHz PHY layer defined as part of the IEEE 802.15.4 standard. The specification requirements for IEEE 802.15.4-compliant transceivers, and the design challenges and practical implementation of a highly-integrated low-power 2.4 GHz transceiver are subsequently discussed. The transceiver uses a direct-conversion receiver with switched antenna diversity and a transmitter using direct closedloop VCO modulation. It integrates a mask-programmable radio controller capable of autonomously performing timing-critical MAC functions, and a sleep timer. Implemented in 0.18 mum RFCMOS technology with a chip area of less than 6 mm², the transceiver achieves a link margin of 99 dB while drawing 16.8 mA and 18 mA from a 1.8 V supply in receive and transmit mode, respectively.     

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector

A jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit is presented. The proposed architecture cascades 2 half-rate CDRs with different loop bandwidth to relax the design bottleneck and the predicted jitter tolerance can be enhanced without sacrificing the jitter transfer. By using a gated digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector may reduce the cost of this architecture and achieve a wide linear range. This CDR circuit has been fabricated in a 0.13 mum CMOS technology and consumes 60 mW from a 1.5 V supply. It occupies an active area of 0.36 mm². The measured rms jitter is 0.96 ps and the peak-to-peak jitter is 7.11 ps for a 10 Gb/s 2⁷-1 PRBS. The measured bit error rate for a 10 Gb/s 2⁷-1PRBS is less than 10^-12.     

A 1 V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications

This paper presents a 1 V RF transceiver for biotelemetry and wireless body sensor network (WBSN) applications, realized as part of an ultra low power system-on-chip (SoC), the Sensiumtrade. The transceiver utilizes FSK/GFSK modulation at a data rate of 50 kbit/s to provide wireless connectivity between target sensor nodes and a central base-station node in a single-hop star network topology operating in the 862-870 MHz European short-range-device (SRD) and the 902-928 MHz North American Industrial, Scientific & Medical (ISM) frequency bands. Controlled by a proprietary media access controller (MAC) which is hardware implemented on chip, the transceiver operates half-duplex, achieving -102 dBm receiver input sensitivity (for 1E-3 raw bit error rate) and up to -7 dBm transmitter output power through a single antenna port. It consumes 2.1 mA during receive and up to 2.6 mA during transmit from a 0.9 to 1.5 V supply. It is fabricated in a 0.13 mum CMOS technology and occupies 7 mm² in a SoC die size of 4 times 4 mm².     

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11- μm CMOS

This paper presents a 20-Gb/s simultaneous bidirectional transceiver using a resistor-transconductor (R-gm) hybrid in standard 0.11-mum CMOS. The R-gm hybrid separates the inbound signal from the signal line voltage and current without using a replica driver. It eliminates the need for precise matching between the replica- and main-driver characteristics, enabling a data rate of 20 Gb/s per differential pair, which is the highest reported for bidirectional signaling. The transceiver occupies 1.0² mm and consumes 260 mW at 20 Gb/s with a bit error rate of less than 10^-12. The area and power overhead due to the hybrid are 0.002 mm² and 7 mW, and correspond to 0.2% and 3% of the total transceiver area and power consumption     

A Fully Integrated 4 × 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology

Optical and electronic building blocks required for DWDM transceivers have been integrated in a 0.13 mum CMOS SOI technology. Using these building blocks, a 4 x 10-Gb/s single-chip DWDM optoelectronic transceiver with 200 GHz channel spacing has been demonstrated. The DWDM transceiver demonstrates an unprecedented level of optoelectronic system integration, bringing all required optical and electronic transceiver functions together on a single SOI substrate. An aggregate data rate of 40 Gb/s was achieved over a single fiber, with a BER of less than 10^-12 and a power consumption of 3.5 W.     

ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network

This paper presents an architecture as well as circuit implementation of a ZigBee modulator/demodulator in the transceiver for personal area network, which is compliant with the physical layer of IEEE standard 802.15.4. A test prototype has been designed and fabricated using 0.18-mum single-poly six-metal CMOS process with core area of 0.16 mm² . The measurement results show that packet error rate (PER) is less than 1% given SNR = 5 dB. The total power consumption is merely 251 muW at a 2.4-MHz system clock.     

A 10-Gb/s CMOS clock and data recovery circuit with a half-ratelinear phase detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm², the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10^-6, with random data input of length 2²³-1. The power dissipation is 72 mW from a 2.5-V supply     

A Passive Switched-Capacitor Finite-Impulse-Response Equalizer

A passive CMOS switched-capacitor finite-impulse-response equalizer is described. A sampling rate of 200 MS/s is achieved by six time-interleaved channels. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data signal. The 4-tap equalizer prototype is fully differential. At 200 MS/s, the equalizer dissipates 19.5 mW, which is virtually all consumed by clock drivers, and occupies an active area of 1.3 mm² in a 0.35 mum CMOS process     

A Power-Efficient Clock and Data Recovery Circuit in 0.18 μm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 mum CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of 0.045 mm² /channel, with the total aggregate data bit rate of 20 Gb/s. The measured FTOL is plusmn3.5% and no error was detected for a 2³¹-1 pseudo-random bit stream (PRBS) input data for 30 minutes, meaning that the bit error rate (BER) is smaller than 10^-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning range and compensated loop gain has been introduced to tune the center frequency of all CDR channels to the desired value.     

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm² per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.     

A power and area efficient CMOS clock/data recovery circuit forhigh-speed serial interfaces

A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm² for the digital PLL and 0.44 mm² for the analog PLL. It can handle an input data rate up to 280 Mb/s     

A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter forserial links

A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8-μm CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3× oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of ~3×3 mm²     

A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1QHDSL transceivers

A 60-MHz 64-tap adaptive finite-impulse-response (FIR) filter chip was fabricated in 1.2-μm CMOS. It can implement either an echo canceler or a decision feedback equalizer for 2B1Q high bit rate digital subscriber line (HDSL) transceivers. The 4.3×4.3 mm², 30000 transistor chip is a completely self-contained adaptive filter which incorporates the least mean square (LMS) algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths, which are often required in high bit rate transceivers. At a 60-MHz clock rate, the echo canceler/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud     

A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors

In this paper, a novel 10-bit A/D converter based on a pipeline-like architecture specific for low-noise, self-triggered sensors, (e.g., X-rays and 7-rays spectrometry) is presented. The main innovative feature of the proposed A/D structure is the concept that, for a sampled input signal, a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal (clock). The conversion is obtained asynchronously propagating the partial conversions and the residues through the various stages. This concept is validated by means of a prototype ADC fabricated in a standard 0.35 mum CMOS technology. The active area is 2.24 mm², and it provides a conversion in 2.5 mus (i.e., it can operate with a 400 kS/s data rate) featuring an ENOB equal to 8.91.     

622-Mb/s Bidirectional SFP Optical Transceiver Using an Integrated WDM Optical Subassembly

The 1.3/1.55-mum bidirectional small form pluggable (SFP) optical transceiver with an integrated wavelength division multiplexing (WDM) subassembly using accurate ceramic blocks has been developed. The WDM subassembly on which a laser diode, a receiver photodiode, a WDM filter, and two microlenses are integrated is only 2.0 times 2.1 times 0.6 mm³ in size and inserted in a TO-CAN package. The SFP transceiver coupled with single-mode fiber has been operated at a 622-Mb/s data rate. The transmitted optical output power is -2.8 dBm and the measured value of sensitivity is -32 dBm at 10^-10 bit-error rate.     

A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrumtransceiver IC [wireless LANs]

In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. The transceiver consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/s. Modulation/demodulation, carrier recovery, PN acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design were performed before layout implementation. The 0.8-μm N-well CMOS chip has a complexity of 56000 transistors with a core area of 3.5×3.5 mm². Power dissipation is 92 and 145 mW at 2.6 and 3.3 V, respectively     

An 85-MHz fourth-order programmable IIR digital filter chip

The authors describe the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-μm CMOS technology. The coefficient and input data word lengths of the filter are 10 b each, and the output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10×10 multiply-add modules are used in this chip. The chip contains 80000 devices in an active area of 14 mm². It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5×10⁹ multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed     

A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/sADC array in 1.2-μm CMOS

A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-μm CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm² and the core of the parallel ADC array occupies an area of 2.7×3.3 mm². The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively     

A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications

This paper presents a low-power wideband signaling (WBS) digital transceiver for data transmission through a human body for body area network applications. The low-power and highspeed human body communication (HBC) utilizes a digital transceiver chip based on WBS and adopts a direct-coupled interface (DCI) which uses an electrode of 50-Omega impedance. The channel investigation with the DCI identities an optimum channel bandwidth of 10 kHz to 100 MHz. The WBS digital transceiver exploits a direct digital transmitter and an all-digital clock and data recovery (CDR) circuit. To further reduce power consumption, the proposed CDR circuit incorporates a low-voltage digitally-controlled oscillator and a quadratic sampling technique. The WBS digital transceiver chip with a 0.25-mum standard CMOS technology has 2-Mb/s data rate at a bit error rate of 1.1 times 10^-7, dissipating only 0.2 mW from a 1-V supply generated by a 1.5-V battery.     

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than ±0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-μm CMOS technology and has an active area of only 0.35 mm²