Novel Delta-Doped InAlGaP/GaAs Heterojunction Bipolar Transistor

The first successful demonstration of a delta-doped InAlGaP/GaAs heterojunction bipolar transistor (HBT) is reported. A comparison to a baseline InAlGaP/GaAs HBT without a delta-doping layer is made. Both of these devices exhibit near-ideal current gain (beta) versus the collector current (I _C) characteristics (i.e., beta independent of I _C) at high currents. The delta-InAlGaP/GaAs HBT exhibits a 40% reduction in offset voltage (V _{CE, offset}) and a 250-mV reduction in knee voltage (V _k) without sacrificing beta compared with the baseline InAlGaP/GaAs HBT. At a higher I _C, the decrease in beta of the InAlGaP/GaAs HBTs with increasing temperature is significantly smaller than the corresponding effect measured in the formerly reported GaAs-based HBTs. The rather temperature-insensitive characteristics of these two InAlGaP/GaAs HBTs originate from their large valence-band discontinuity (DeltaE _V) at the emitter-base (E-B) junction. Furthermore, at intermediate base current I _B levels (0.4-1.6 mA), V _{CE, offset} falls as I _B increases, which is a trend contrary to that of most HBTs in the literature. Finally, the experimental dependence of V _{CE, offset} on temperature, I _B, and the effective barrier height at the E-B junction is explained with reference to an extended large-signal model.     

Noise studies in internal field emission diodes

The breakdown process of a zener diode in reverse direction is governed by internal field emission at low voltage and by impact ionization at higher voltage. For breakdown voltage in the transition range between 3 and 6 V, both physical processes appear in combination. Measuring the I–V characteristic and the noise current fluctuations spectral density it is possible to show the zener current multiplication by the multiplication effect described by Tager. In addition the I–V characteristic can be written empirically I = Vⁿ.     

Electrical properties of W/Si interfaces with embedded Ge/Si islands

In this work, we investigated electrical and morphological properties of W/p-type Si Schottky diodes with intentional inhomogeneities introduced by macroscopic Ge-islands embedded beneath the interface. The Si-cap layer thickness (or the island-distance to the interface) was progressively reduced by successive chemical etching cycles. Electrical characterizations were achieved through reverse current–voltage (I–V) at room temperature and forward I–V measurements as a function of the temperature. In parallel, Rutherford backscattering spectroscopy analyses were performed to follow the Si-cap/Ge islands chemical thinning down with increasing the number of etching cycles. In addition, the comparison of topographical and electrical properties of the etched silicon-cap layer was carried out by conductive atomic force microscopy analyses with a nanometer-scale resolution. Our results indicate that the areas on the top of islands exhibit lower resistance than those which covered the wetting layer. This lateral variation of resistance at the surface of the semiconductor may correspond to Schottky barrier height inhomogeneities observed on broad area I–V characteristics of Schottky contacts.     

Optically controlled current-voltage characteristics of ion-implanted MESFETs

Optically controlled MESFETs are useful as optical devices for optical communications, and as photodetectors. In this paper, a theoretical model for the I–V characteristics of these MESFETs is presented. The model considers the nonuniform Gaussian doping for ion-implanted channels. It takes both the photogenerated carriers as well as the doping generated residual carriers into account. It is noted that the density of photogenerated carriers in the channel due to diffusion is much less than that due to drift. Treatment both under gradual channel approximation and saturation velocity approximation has been presented. The gradual channel and the velocity saturation approximations are applied to study the I–V characteristics of long-channel and short-channel MESFETs, respectively. Results for both long-channel and short-channel MESFETs indicate that drain saturation current and transconductance can be improved by properly fixing the optical flux, and the absorption coefficient of the material.     

Analysis of I–V measurements on PtSi-Si Schottky structures in a wide temperature range

I–V Measurements on PtSi-Si Schottky structures in a wide temperature range from 90 to 350 K were carried out. The contributions of thermionic-emission current and various other current-transport mechanisms were assumed when evaluating the Schottky barrier height Φ₀. Thus the generation-recombination, tunneling and leak currents caused by inhomogeneities and defects at the metal-semiconductor interface were taken into account.

Taking the above-mentioned mechanisms and their temperature dependence into consideration in the Schottky diode model, an outstanding agreement between theory and experiment was achieved in a wide temperature range.

Excluding the secondary current-transport mechanisms from the total current, a more exact value of the thermionic-emission saturation current I_te and thus a more accurate value ofΦ_b was reached.

The barrier height Φ_b and the modified Richardson constant A^** were calculated from the plot of thermionic-emission saturation current I_te as a function of temperature too. The proposed method of finding Φ_b is independent of the exact values of the metal-semiconductor contact area A and of the modified Richardson constant A^**. This fact can be used for determination of Φ_b in new Schottky structures based on multicomponent semiconductor materials.

Using the experimentally evaluated value A^** = 1.796 × 10⁶ Am⁻²K⁻² for the barrier height determination from I–V characteristics the value of Φ_b = 0.881 ± 0.002 eV was reached independent of temperature.

The more exact value of barrier height Φ_b is a relevant input parameter for Schottky diode computer-aided modeling and simulation, which provided a closer correlation between the experimental and theoretical characteristics.     

Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

Procedure for determining diode parameters at very low forward voltage

A technique is proposed to extract the reverse saturation current parameter and ideality factor of semiconductor junctions from the low forward voltage region of the device’s characteristics. The method involves performing a mathematical operation on the experimental data that allows to calculate the parameters at values of forward current smaller than the reverse saturation current. The procedure was tested and its accuracy verified on synthetic I–V characteristics, with and without added simulated experimental error or noise. Good agreement is obtained between the parameters used in modeling and the extracted values. The procedure was also applied to experimentally measured I_B–V_BE characteristics of a real power BJT.     

Design and fabrication of multiple-valued multiplexer using negative differential resistance circuits and standard SiGe process

The design of a four-valued multiplexer using the negative differential resistance (NDR) circuit is demonstrated. The NDR circuit used in this work is made of the Si-based metal–oxide–semiconductor field-effect-transistor (MOS) and the SiGe-based heterojunction bipolar transistor (HBT). However we can obtain the NDR characteristic in its combined I–V curve by suitably arranging the MOS parameters. This novel multiplexer is made of MOS–HBT–NDR-based decoders and inverters. The fabrication is based on the standard 0.35 μm SiGe BiCMOS process.     

A complete analytical model of GaN MESFET for microwave frequency applications

A simple physics-based analytical model for a non-self-aligned GaN MESFET suitable for microwave frequency applications is presented. The model includes the effect of parasitic source/drain resistances and the gate length modulation. The model is then extended to evaluate I–V and C–V characteristics, transconductance, cut-off frequency, transit time, RC time constant, optimum noise figure and maximum power density. The transconductance of about 21 mS/mm is obtained for GaN MESFET using the present theory in comparison to 23 mS/mm of the reported data. The cut-off frequency of more than 1 GHz, optimum noise figure of 6 dB and maximum output power density of more than 1 W/mm are predicted.     

Temperature-dependence of steady-state characteristics of SCR-type ESD protection circuits

Experimental analysis of the temperature-dependent I–V characteristics of various SCR (Silicon-Controlled Rectifier) electrostatic discharges (ESD) protection circuits have been carried out. These circuits include diode-chain-triggering SCR (DCTSCR), low-voltage zener diode trigger SCR (ZDSCR), low-voltage trigger SCR (LVTSCR) and gate-coupled low-voltage trigger SCR (GCSCR) circuits. The ZDSCR uses the zener breakdown mechanism of a reverse-biased p⁺–n⁺ diode as a trigger mechanism, the DCTSCR uses the current flowing through forward-biased diode chain as a trigger mechanism, the LVTSCR uses the grounded-gate MOSFET breakdown current as the trigger mechanism and the steady-state I–V characteristics of GCSCR also uses the avalanche breakdown as a triggering mechanism. The trigger voltage can decrease or increase with increasing temperature depending upon the triggering mechanism used in the circuit, however the holding voltages of these SCRs decrease with increasing temperature.     

Breakdown degradation associated with elementary screw dislocations in 4H-SiC pn junction rectifiers

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector>2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector=1c with no hollow core) in densities on the order of thousands per cm², nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current–voltage (I–V) characteristics of 4H-SiC p⁺n diodes. First, synchrotron white beam X-ray topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p⁺n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I–V knee, and no visible concentration of breakdown current. In contrast, devices that contained at least one elementary screw dislocation exhibited 5–35% reduction in breakdown voltage, a softer breakdown I–V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices.     

Analytical expressions for the static MOS transistor characteristics based on the gradual channel model

Analytical solutions are derived from Pao and Sah's double integral formula for the theoretical static I–V characteristics of MOS transistors including both the diffusion and drift currents based on the gradual channel model. Expressions for the entire saturation, non-saturation and low level current regions are given, while the specific importance of the theory is seen in the cross-over region between low level and normal operation. Reddi and Sah's formula for channel shrinkage is modified and included to account for the small drain conductance in the saturation region by taking the drain avalanche breakdown voltage into consideration. The solutions are compared with experimental data, and the effectiveness and the limit of the theory is quickly examined.     

A detailed investigation of heterojunction transport using arigorous solution to the Boltzmann equation

A detailed study of electron transport across an Np⁺ heterojunction diode is performed using a rigorous numerical solution to the Boltzmann equation. Results are presented for the I-V characteristic and the average electron energy, temperature, energy flux, and quasi-Fermi levels as a function of position. Comparison with a simple analytical treatment shows good agreement for the current and quasi-Fermi level splitting versus bias. The distribution functions near the heterojunction interface are also investigated and found to be distinctly non-Maxwellian. Finally, the results are used to examine the boundary conditions of hydrodynamic quantities at the heterojunction     

An analytical model for the power bipolar-MOS transistor

This paper presents an analytical model for the I–V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4–10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in V_F. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase V_F but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.     

A new empirical large-signal model for enhancement-mode AlGaAs/InGaAs pHEMTs

We propose a new large-signal model for AlGaAs/InGaAs pHEMTs, which can simulate the device microwave output power, non-linear characteristics at arbitrary bias points. This model includes a new drain current equation, which is extracted from its derivatives. In addition, gate-to-source and gate-to-drain capacitances are also characterized versus the function of gate and drain biases. The parameter extraction procedure is addressed for the enhancement-mode pHEMTs, which offers an attractive solution for handset power amplifier application because of its positive bias characteristics. Finally, measured and model-predicted dc I–V, S-parameters, and power performance have been compared.     

Effect of Channel Width Shortening on the Stability of a-Si:H/nc-Si:H Bilayer Thin-Film Transistors

The static bias-stress-induced degradation of hydrogenated amorphous/nanocrystalline silicon bilayer bottom-gate thin-film transistors is investigated by monitoring the turn-on voltage (V _on) and on-state current (I _on) in the linear region of operation. Devices of constant channel length 10 mum and channel width varying from 3 to 400 mum are compared. The experimental results demonstrate that the device degradation is channel-width dependent. In wide channel devices, substantial degradation of V _on is observed, attributed to electron injection into the gate dielectric, followed by I _on reduction due to carrier scattering by the stress-induced gate insulator trapped charge. With shrinking the channel width down to 3 mum, the device stability is substantially improved due to the possible reduction of the electron thermal velocity during stress or due to the gate insulator quality uniformity over small dimensions.     

Theory of switching phenomena in metal/semi-insulator/n-p silicon devices

The theory of switching is presented for a structure consisting of a p⁺-n junction and a metal electrode separated from the N-section of the p⁺-n junction by a semi-insulating (leaky) layer.

When a negative bias is applied to the electrode, the section of the n-layer under the electrode goes into deep depletion. In this mode, the current through the device is limited by generation in the deeply depleted region. This is the high-impedance or OFF state of the device.

At a sufficiently high voltage, the switching voltage, V_s, the p⁺-n junction is turned on by either avalanching in the n-layer or by the deep-depletion region extending through to the p⁺-n region (punch-through). When the junction turns on, the n-section goes from deep-depletion towards inversion. Thus, the voltage across the device decreaseswith a concomitant increase in the current through the device. This is the switching mode. The switching voltage may be tailored by varying the doping and/or width of the n-section.

Following switching, the device comes into the steady-state when the current through the insulating layer is equal to the current flowing across the p⁺-n junction. The I-V characteristic of this highly conducting (ON state) mode is determined principally by the I-V characteristic of the semi-insulating film. By suitable choice of material this portion of the characteristic can approach zero dynamic impedance, i.e. a near-vertical characteristic, characterized by a low holding voltage. Capacitance and switching characteristics of the device are also discussed.     

On the effect of non-degenerate doping of polysilicon gate in thin oxide MOS-devices—Analytical modeling

A one-dimensional model of the polysilicon-gate-oxide-bulk structure is presented in order to analyze the implanted gate MOS-devices. The influence of the ionized impurity concentration in the polysilicon-gate near the oxide and the charge at the polysilicon-oxide interface on the flat-band voltage, threshold voltage, inversion layer charge and the quasi-static C–V characteristic is quantitatively studied. The calculations show a considerable degradation of the inversion layer charge due to the voltage drop in the gate, especially in thin oxide devices. The calculated quasi-static C–V curves agree with the recently published data of implanted gate devices.     

Effect of oxide resistance on the characterization of interface trap density in MOS structures

The oxide resistance in a practical MOS capacitor is generally not high enough to be negligible in the evaluation of interface trap density based on the qruasi-static capacitance-voltage (C–V) curve. The importance of the effects of oxide resistance ranging from 10¹³ to 10¹⁶ Ω on the C–V curve and the corresponding interface trap density is theoretically shown. To obtain the oxide resistance in MOS structures the newly reported charge-then-decay method is suggested. From the oxide resistance found, one can compare the distribution curves of interface trap density before and after removing the oxide resistance effect. It is found that the results obtained after removing the oxide resistance effect are more consistent than those without removing it. It addition, the removal of the oxide resistance effect for a sample having a hysteresis C–V behavior is also discussed.     

A circuit-compatible analytical device model for ballistic nanowire transistors

Silicon nanowire transistors (SNWTs) have attracted broad attention as a promising device structure for future integrated circuits. Silicon nanowires with a diameter as small as 2 nm and having high carrier mobility have been achieved. Consequently, to develop TCAD tools for SNWT design and to model SNWT for circuit-level simulations have become increasingly important. This paper presents a circuit-compatible closed-form analytical model for ballistic SNWTs. Both the current–voltage (I–V) and capacitance–voltage (C–V) characteristics are modeled in terms of device parameters and terminal voltages. Such a model can be efficiently used in a conventional circuit simulator like SPICE to facilitate transistor-level simulation of large-scale nanowire or mixed nanowire-CMOS circuits and systems.