Adaptive coded modulation with receive antenna diversity and imperfect channel knowledge at receiver and transmitter

Unifying and generalizing the works of Cai and Giannakis and Oien et al., the performance of an adaptive trellis-coded modulation system where receive antenna diversity is implemented by means of maximum ratio combining is analyzed and optimized. As in the work of Cai and Giannakis, the analysis is done in the presence of both estimation and prediction errors. Rayleigh fading on each subchannel is considered, with the estimation and prediction being performed independently on each subchannel. The system optimization process is done in such a way that the throughput is maximized under a bit-error-rate (BER) constraint. The numerical example employs a Jakes-fading spectrum and shows how the power should be distributed between pilot and data symbols and how often pilot symbols should be transmitted for maximum throughput under an instantaneous (with respect to the predicted channel) BER constraint.     

A low-power CMOS super-regenerative receiver at 1 GHz

A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35-μm CMOS process is described. The receiver includes a low-noise amplifier, a super-regenerative oscillator, an envelope detector, an AGC circuit with sample/hold function, and a baseband amplifier. The die surface is equal to 0.25 mm ². The power consumption is less than 1.2 mW at V_DD=1.5 V. A 100-kHz sawtooth quench signal is used to achieve a rejection of -36 dB at 500 KHz from the central frequency     

应用于WLAN的小型微带天线

为了满足手机无线局域网(WLAN)通信技术的要求,设计了一个三频段单极子贴片天线,通过2个L形支路产生双频辐射。并用软件对该天线进行仿真优化,实现了2.4 GHz、5.2 GHz和5.8 GHz三频段的同时工作,而且该天线结构简单,由L形贴片组合形成,体积小,所占面积为14.5 mm×16.5 mm。仿真结果表明,该天线的尺寸和性能可以在手机WLAN通信系统得到良好的应用     

Monolithic InGaP-GaAs HBT receiver front-end with 6 mW DC power consumption for 5 GHz band WLAN applications

A very low power consumption (6 mW) 5 GHz band receiver front-end using InGaP-GaAs HBT technology is reported. The receiver front-end is composed of a cascode low noise amplifier followed by a double-balanced mixer with the RF transconductor stage placed above the Gilbert quad for direct-coupled connection. The RF band of this receiver front-end is set to be 5.2 GHz, being downconverted to 1 GHz IF frequency. Input-return-loss (S/sub 11/) in RF port smaller than -12 dB and excellent power-conversion-gain of 35.4 dB are achieved. Input 1 dB compression point (P/sub 1dB/) and input third-order intercept point (IIP3) of -24 and -3 dBm, respectively, are also achieved.     

Transconductance amplifier with low-power consumption

A modified transconductance amplifier with low harmonic distortion and high current efficiency is proposed. It can be used in high-frequency applications up to 10 MHz. Each half of the transconductor differential input stage consists of a pair of transistors in saturation and linear regimes with a voltage feedback loop. Results of theoretical analysis are confirmed by SPICE simulations.     

Compact uniplanar antenna for WLAN applications

A compact dual-band uniplanar antenna for operation in the 2.4/5.2/5.8 GHz WLAN/HIPERLAN2 communication bands is presented. The dual-band antenna is obtained by modifying one of the lateral strips of a slot line, thereby producing two different current paths. The antenna occupies a very small area of 14.5times16.6 mm² including the ground plane on a substrate having dielectric constant 4.4 and thickness 1.6 mm at 2.2 GHz. The antenna resonates with two bands from 2.2 to 2.52 GHz and from 5 to 10 GHz with good matching, good radiation characteristics and moderate gain     

A low-power all-digital FSK receiver for space applications

A frequency-shift keying (FSK) receiver has been designed for deep space applications which exhibits potential for ultra low power performance. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-bit data processing together with a discrete Fourier transform-based detection scheme to enable power consumption dramatically lower than implementations reported in the literature. Novel and power-efficient algorithms are derived for frequency and timing tracking. Most of the power saving techniques are applicable to a variety of applications, but some are achieved by taking advantage of the asymmetric power constraints for the receiver and the transmitter as well as the absence of adjacent channel interferers. The worst-case bit-error rate (BER) performance of the receiver is just 2.5 dB below that of the optimal uncoded noncoherent FSK receiver at a BER of 10^-6 and better for lower BERs     

一种集成电长度补偿功能的C频段五通道接收组件

介绍了一种C频段五通道接收组件的设计方法。阐述了接收组件的工作原理,给出了功能实现框图,分析了电长度补偿单元、通道选择单元、幅相控制单元、信号合成单元共4个部分的设计方案。采用盘旋同轴线方案实现了电长度补偿,补偿最大值达635o。接收组件集成了限幅、通道选择、5位移相、5位衰减、电长度补偿、信号合成、电压转换等功能。接收组件的测试结果为噪声系数3.5 dB,增益25 dB,输入输出驻波比小于1.5：1,总功耗780 mW。     

Ultracompact reflective-type phase shifter MMIC at C-band with360° phase-control range for smart antenna combining

An ultracompact reflective-type monolithic microwave integrated circuit (MMIC) phase shifter is presented, fabricated using a commercial 0.6-μm GaAs MESFET process. The circuit has been developed for low-cost smart antenna receivers, operating in accordance to the IEEE 802.11a and the high-performance radio local area network (HIPERLAN) wireless network standards at C-band. Capacitance control, required for phase control, is performed by usual MESFETs with capacitance control ratios (C_max/C_min) of less than four. The impact of the reflective terminations on the maximum phase-control range and the corresponding loss is discussed. This investigation comprises single capacitive terminations, single resonated terminations, and terminations with two resonated loads-in parallel (DRL). With the DRL terminations, phase-control ranges of over 360° have been reached even with such limited capacitance control ranges. A transformation network is proposed for the DRL termination to reduce loss and loss variations. In this configuration, maximum signal losses of 9 and 3 dB, and 1-dB input compression points of higher than 2 and 8 dBm were measured for the phase shifter at 5.2 GHz within phase-control ranges of 360° and 90°, respectively. The branch-line coupler of the phase shifter has been realized by using lumped elements, thereby minimizing the circuit size. The total chip area is only 0.9 mm², which to our knowledge is the smallest size for a passive reflective-type phase shifter with 360° phase-control range reported to date     

Low-cost low-power UHF RFID tag with on-chip antenna

chip antenna is realized by adjusting the rectifier input impedance. Measurements show that the presented tag can achieve a communication range of 1 cm with 1 W reader output power using a 1 × 1 cm2 single-turn loop reader antenna.     

集成片上天线的低成本低功耗超高频射频识别标签

This paper presents an EPC Class 1 Generation 2 compatible tag with on-chip antenna implemented in the SMIC 0.18 μm standard CMOS process.The UHF tag chip includes an RF/analog front-end, a digital baseband, and a 640-bit EEPROM memory.The on-chip antenna is optimized based on a novel parasitic-aware model.The rectifier is optimized to achieve a power conversion efficiency up to 40% by applying a self-bias feedback and threshold compensation techniques.A good match between the tag circuits and the on-chip antenna is realized by adjusting the rectifier input impedance.Measurements show that the presented tag can achieve a communication range of 1 cm with 1 W reader output power using a 1 × 1 cm2 single-turn loop reader antenna.     

C-band orthomode transducer for compact and broadband antenna feeders

The design and evaluation of a compact C-band orthomode transducer for dual polarisation satellite communications is presented, covering the bands 3.7-4.2 GHz and 5.925-6.425 GHz (54% of fractional bandwidth separation). Over such a broadband, the main difficulty is to obtain a compact structure able to fulfil the stringent satellite specifications with minimum longitudinal length. The proposed configuration, validated with a tested prototype, also reduces the number of connections and parts in the fabrication, decreasing the passive intermodulation risk and the mass and volume.     

Printed diversity monopole antenna for WLAN operation

A printed diversity monopole antenna for WLAN operation in the 2.4 GHz band is presented. The antenna comprises two orthogonal linear monopoles placed symmetrically with respect to a T-shaped ground plane between them. The antenna has two highly decoupled ports and can provide spatial diversity to combat the multipath interference problem.     

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixer's IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.     

Dual-band toroidal beam antenna for WLAN communications

A novel dual-band toroidal beam antenna for wireless local area network (WLAN) communications is presented. The antenna mainly consists of six dual-band inverted-L radiating elements and a twosection six-way microstrip power divider. By inserting slots into the radiating elements, two resonant frequencies are achieved at WLAN bands. By using the two-section six-way power divider, the six radiating elements are excited with equal amplitude and phase at the two working frequency bands. A prototype has been constructed and tested. Good toroidal beam radiation patterns for 2.4 and 5.2 GHz bands are obtained.     

Compact dielectric resonator antenna for WLAN applications

A new dielectric resonator antenna (DRA) with reduced size for WLAN applications is presented. The proposed antenna consists of a rectangular dielectric resonator with partial vertical and horizontal metallisations which is coupled to a microstrip line through a rectangular aperture in the ground plane. A 9.6 reduction coefficient is obtained compared to the volume of an equivalent isolated DRA. An experimental 12% bandwidth is also achieved in spite of the compact size.     

A low-power baseband receiver IC for frequency-hopped spreadspectrum communications

A baseband receiver IC which will be incorporated into a low-power frequency-hopped spread spectrum (FH/SS) transceiver for 902-928 MHz ISM band applications is presented. The chip performs noncoherent binary/quaternary frequency shift keying (FSK) demodulation, equal-gain diversity combining of dual antenna branches, and symbol and frequency synchronization. The chip also accommodates variable data rates from 2 to 160 kb/s, programmable hop rates, and tunable bandwidth Loop filters. The core area of the 1-μm CMOS chip is 3.9 mm×3.9 mm with a power consumption of 4.5 mW at 10 MHz from a 3-V supply. A baseband transceiver system utilizing this receiver chip for the prototype handset to demonstrate a point-to-point communication link is also described. Two XILINX FPGA chips were used to implement the remainder of the baseband transceiver functions, including frequency control logic for FSK modulation, acquisition control, data framing, symbol interleaving and deinterleaving, and interface control for data and voice     

一款低功率下具有高效率的多模多频功率放大器

越来越多的移动通信协议要求射频功率放大器在低功率模式下具有高效率和低工作电流,为了满足这种需求,本文提出了一种全集成的多模多频射频功率放大器模块设计。本设计通过双路径的功率放大器实现了高功率、中功率和低功率三种模式,并且模块内部没有任何用于模式选择的串联开关。在不同功率模式下,通过最优化负载设计,不仅极大程度的降低了芯片的工作电流,而且实现了良好的工作性能。本设计采用InGaP/GaAs异质结双极晶体管工艺和0.18um的互补金属氧化物半导体工艺完成流片。芯片的实际测试结果显示在低功率模式下,该射频功率模块仅3mA的静态电流,并且在1.7-2.0 GHz带宽范围内高中低功率模式都实现了良好的射频性能,在高功率模式下,输出功率28dBm时,实现了至少39.4% 的功率附加效率和-40 dBc邻道泄漏比;在中功率模式下,输出功率17 dBm时,实现了至少21.3% 的功率附加效率和-43 dBc邻道泄漏比;在低功率模式下,输出功率8 dBm时,实现了至少18.2% 的功率附加效率和-40 dBc邻道泄漏比。     

A low-power multirate differential PSK receiver for space applications

Wireless communication for deep-space and satellite applications needs to accommodate the Doppler shift caused by the movement of the space vehicle and should consume low power to conserve the onboard power. A low-power phase-shift keying (PSK) receiver has been designed for such applications. The receiver employs double differential detection to be robust against Doppler shift and uses subsampling with a 1-bit A/D converter and digital decimation architecture at the front end to achieve low-power consumption. The receiver is also designed to be programmable to operate using single-stage differential detection instead of double-stage differential detection at low Doppler rates to obtain optimum performance. Furthermore, the baseband can be employed in either direct subsampling or intermediate frequency (IF)-sampling front ends. Both front ends offer minimal power consumption and differ from traditional types by replacing some conventional analog components such as a voltage-controlled oscillator, mixer, or phase-locked loop with their digital counterparts. This eliminates problems due to dc offset, dc voltage drifts, and low-frequency (LF) noise. The paper also includes a brief discussion of the nonidealities existing in real applications. The proposed phase shift keying (PSK) receiver supports a wide range of data rates from 0.1-100 Kbps and has been implemented in a CMOS process.     

带温度补偿的低功耗CMOS环形压控振荡器设计

基于UMC 65 nm CMOS工艺,设计了一款应用于锁相环频率综合器中的带温度补偿的低功耗CMOS环形压控振荡器。环形压控振荡器采用3级交叉耦合延时单元构成。仿真结果表明,压控振荡器输出频率范围为735~845 MHz;在温度补偿下,温度变化从-60~100oC时,振荡器输出频率漂移中心频率790 MHz±10 MHz;当振荡频率为790 MHz时,在偏离其中心频率1 MHz处,压控振荡器的相位噪声为-99 d Bc/Hz;1.2 V电源供电情况下,压控振荡器的功耗为0.96 m W;版图面积约为0.005 mm2。