A low-power integrated tuner for cable telephony applications

This paper describes an integrated tuner for cable telephony in a 0.35 /spl mu/m, 27 GHz SOI BiCMOS technology. The IC integrates a complete dual-conversion signal path including upconverter, downconverter, variable-gain amplifier, LO synthesizers with fully integrated voltage-controlled oscillators, gain control circuitry, as well as digital calibration and interface circuits. It accepts signals in the 200-880 MHz band and produces a 44 MHz IF. Drawing 168 mA from a 3 V supply, the tuner system has a worst case noise factor of 7.3 dB, system phase noise below -78 dBc/Hz at a 10 kHz offset, spurs below -42 dBc for 137 5 dBmV input channels, a gain of 60 dB, and gain control range of 68 dB. The 13 mm/sup 2/ IC meets specifications across an outdoor temperature range of -40/spl deg/C to 100/spl deg/C in production lots.     

Ultra-wideband SiGe low-noise amplifier

A low-noise amplifier (LNA) for ultra-wideband (UWB) is presented. The LNA, consisting of two gain stages in multiple feedback loops, achieves a flat power gain of a nominal 20 dB and a noise figure of 2.8-4.7 dB over the 3.1-10.6 GHz UWB band. Implemented in a 0.25 /spl mu/m SiGe BiCMOS process, the amplifier occupies 0.34 mm/sup 2/ and draws 11 mA from a 2.7 V supply.     

Plug-in type 1.3-/spl mu/m fiber amplifier module for rack-mounted shelves

We have successfully developed a plug-in type PDFA module for rack mounted shelves which is assembled on a printed-board. In this module, we use a newly developed Pr/sup 3+/-doped high-NA PbF/sub 2//InF/sub 3/-based fluoride fiber and wavelength stabilized 1.017-/spl mu/m laser diodes (LDs). We have obtained a small-signal gain of 24 dB and a noise figure of 6.6 dB at 1.30 /spl mu/m with an LD drive current of 240 mA/spl times/2. We achieved an output power of 10 dBm with a signal input power of 0 dBm. The total power consumption of this module, including that of a Peltier cooler, was 3.5 W when the LD drive current was 240 mA/spl times/2.     

Baseband stage for WCDMA direct conversion receiver with high dynamic range and accurate temperature compensation

A highly integrated baseband stage, which adopts a new configuration for the wideband code-division multiple access (WCDMA) direct conversion receiver (DCR), is described. The baseband stage satisfies all requirements of the WCDMA DCR and consists of opamp-RC channel select filters and variable gain amplifiers with linear-in-dB gain control. It achieves a high dynamic range of 85 dB with /spl plusmn/1.5 dB accuracy over a temperature variation from -25 to 85/spl deg/C, 16.5 nV//spl radic/Hz input-referred noise, +20 dBV out-of-band IIP3 and +70 dBV out of band IIP2. The baseband stage is fabricated using a 0.35 /spl mu/m SiGe BiCMOS process and consumes a total current of 11 mA/CH from a 2.7 V supply.     

A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98 dB with 2 dB gain steps and is controlled by 6-bit gain control bits for a 3 V power supply. It has been fabricated in a 0.5 /spl mu/m 15 GHz f/sub T/ Si BiCMOS process and draws 13 mA. The active die area taken up by the circuit is 400 /spl mu/m /spl times/ 1170 /spl mu/m. A noise figure (NF) of 4.9 dB was measured at the maximum gain setting. In addition, an analysis of the bias current generation to provide dB-linear gain control is presented.     

DC, RF, and microwave noise performances of AlGaN/GaN HEMTs on sapphire substrates

High-performance AlGaN/GaN high electron-mobility transistors with 0.18-/spl mu/m gate length have been fabricated on a sapphire substrate. The devices exhibited an extrinsic transconductance of 212 mS/mm, a unity current gain cutoff frequency (f/sub T/) of 101 GHz, and a maximum oscillation frequency (f/sub MAX/) of 140 GHz. At V/sub ds/=4 V and I/sub ds/=39.4 mA/mm, the devices exhibited a minimum noise figure (NF/sub min/) of 0.48 dB and an associated gain (Ga) of 11.16 dB at 12 GHz. Also, at a fixed drain bias of 4 V with the drain current swept, the lowest NFmin of 0.48 dB at 12 GHz was obtained at I/sub ds/=40 mA/mm, and a peak G/sub a/ of 11.71 dB at 12 GHz was obtained at I/sub ds/=60 mA/mm. With the drain current held at 40 mA/mm and drain bias swept, the NF/sub min/,, increased almost linearly with the increase of drain bias. Meanwhile, the Ga values decreased linearly with the increase of drain bias. At a fixed bias condition (V/sub ds/=4 V and I/sub ds/=40 mA/mm), the NF/sub min/ values at 12 GHz increased from 0.32 dB at -55/spl deg/C to 2.78 dB at 200/spl deg/C. To our knowledge, these data represent the highest f/sub T/ and f/sub MAX/, and the best microwave noise performance of any GaN-based FETs on sapphire substrates ever reported.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

A 3.1- to 8.2-GHz zero-IF receiver and direct frequency synthesizer in 0.18-/spl mu/m SiGe BiCMOS for mode-2 MB-OFDM UWB communication

A direct conversion receiver for ultra-wideband (UWB) applications operates for 3.1 to 8.2 GHz and gives a noise figure of 3.3 to 4.1 dB and a conversion gain of 52 dB. The chip includes the RF receive chain and a 16-GHz quadrature VCO to generate seven carrier frequencies from 3.4 to 7.9 GHz. The circuit was fabricated in a 0.18-/spl mu/m SiGe BiCMOS process and consumes 88 mA from a 2.7-V supply.     

2 V-operated InGaP-AlGaAs-InGaAs enhancement-mode pseudomorphic HEMT

A low-voltage single power supply enhancement-mode InGaP-AlGaAs-InGaAs pseudomorphic high-electron mobility transistor (PHEMT) is reported for the first time. The fabricated 0.5/spl times/160 /spl mu/m/sup 2/ device shows low knee voltage of 0.3 V, drain-source current (I/sub DS/) of 375 mA/mm and maximum transconductance of 550 mS/mm when drain-source voltage (V/sub DS/) was 2.5 V. High-frequency performance was also achieved; the cut-off frequency(F/sub t/) is 60 GHz and maximum oscillation frequency(F/sub max/) is 128 GHz. The noise figure of the 160-/spl mu/m gate width device at 17 GHz was measured to be 1.02 dB with 10.12 dB associated gain. The E-mode InGaP-AlGaAs-InGaAs PHEMT exhibits a high output power density of 453 mW/mm with a high linear gain of 30.5 dB at 2.4 GHz. The E-mode PHEMT can also achieve a high maximum power added efficiency (PAE) of 70%, when tuned for maximum PAE.     

60-GHz SOI CMOS traveling-wave amplifier with NF below 3.8 dB from 0.1 to 40 GHz

In this paper, the design and the results of a CMOS traveling-wave amplifier (TWA) optimized for minimum noise figure is presented. Design tradeoffs and optimization guidelines for maximum operation frequency, gain and minimum noise are discussed by means of analytical calculations and simulations. The MMIC is fabricated using digital 90-nm silicon on insulator (SOI) technology and requires a chip area of only 0.3 mm/sup 2/. At a supply voltage of 2 V and a supply current of 66 mA, a gain of 9.7 dB/spl plusmn/1.6 dB is measured over a frequency range from 10 to 59 GHz. Toward dc, the gain increases up to 16 dB. The unity gain cutoff frequency is 71 GHz. At 20 and 40 GHz, the circuit has a 1-dB output compression point of 12.5 and 9.5 dBm, respectively. From 0.1 to 40 GHz, a noise figure below 3.8 dB is measured. The results are achieved at source/load impedances of 50 /spl Omega/ and include the pad parasitics. To the author's knowledge, the TWA has by far the lowest noise figure achieved for a silicon-based amplifier with comparable bandwidth.     

High-dynamic-range VGA with temperature compensation and linear-in-dB gain control

This paper presents the design and measured performance of a novel intermediate-frequency variable-gain amplifier for Wideband Code-Division Multiple Access (WCDMA) transmitters. A compensation technique for parasitic coupling is proposed which allows a high dynamic range of 77 dB to be attained at 400 MHz while using a single variable-gain stage. Temperature compensation and decibel-linear characteristic are achieved by means of a control circuit which provides a lower than /spl plusmn/1.5 dB gain error over full temperature and gain ranges. The device is fabricated in a 0.8-/spl mu/m 46 GHz f/sub T/ silicon bipolar technology and drains up to 6 mA from a 2.7-V power supply.     

A 0.13 /spl mu/m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier

This paper presents a fully integrated CMOS receiver front-end based on a direct conversion architecture for UMTS/802.11b-g and a low-IF architecture at 100 kHz for DCS1800. The two key building blocks are a multiband low-noise amplifier (LNA) that uses positive feedback to improve its gain and a highly linear mixer. The front-end, integrated in a 0.13 /spl mu/m CMOS process, exhibits a minimum noise figure of 5.2 dB, a programmable gain that can be varied from 13.5 to 28.5 dB, an IIP3 of more than -7.5 dBm and an IIP2 better than 50 dBm. The total current consumption is 20mA from a 1.2V supply.     

Internally matched, ultralow DC power consumption CMOS amplifier for L-band personal communications

An internally matched, extremely low operation voltage amplifier monolithic microwave integrated circuit (MMIC) has been implemented in a 0.35-/spl mu/m silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology for L-band personal communications. At 1.6 GHz the MMIC amplifier has a gain of 6.4 dB and a noise figure of 4.8 dB at a drain voltage of 0.6 V and a current of 2 mA. The MMIC amplifier exhibits a Gain/Power quotient as high as 5.33 dB/mW, which we believe is the highest recorded for Si CMOS MMIC technology.     

26-42 GHz SOI CMOS low noise amplifier

A complementary metal-oxide semiconductor (CMOS) single-stage cascode low-noise amplifier (LNA) is presented in this paper. The microwave monolithic integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator (SOI) technology. All impedance matching and bias elements are implemented on the compact chip, which has a size of 0.6 mm /spl times/ 0.3 mm. The supply voltage and supply current are 2.4 V and 17 mA, respectively. At 35 GHz and 50 /spl Omega/ source/load impedances, a gain of 11.9 dB, a noise figure of 3.6 dB, an output compression point of 4 dBm, an input return loss of 6 dB, and an output return loss of 18 dB are measured. The -3-dB frequency bandwidth ranges from 26 to 42 GHz. All results include the pad parasitics. To the knowledge of the author, the results are by far the best for a silicon-based millimeter-wave LNA reported to date. The LNA is well suited for systems operating in accordance to the local multipoint distribution service (LMDS) standards at 28 and 38 GHz and the multipoint video distribution system (MVDS) standard at 42 GHz.     

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.     

High microwave and noise performance of 0.17-/spl mu/m AlGaN-GaN HEMTs on high-resistivity silicon substrates

AlGaN-GaN high-electron mobility transistors (HEMTs) based on high-resistivity silicon substrate with a 0.17-/spl mu/m T-shape gate length are fabricated. The device exhibits a high drain current density of 550 mA/mm at V/sub GS/=1 V and V/sub DS/=10 V with an intrinsic transconductance (g/sub m/) of 215 mS/mm. A unity current gain cutoff frequency (f/sub t/) of 46 GHz and a maximum oscillation frequency (f/sub max/) of 92 GHz are measured at V/sub DS/=10 V and I/sub DS/=171 mA/mm. The radio-frequency microwave noise performance of the device is obtained at 10 GHz for different drain currents. At V/sub DS/=10 V and I/sub DS/=92 mA/mm, the device exhibits a minimum-noise figure (NF/sub min/) of 1.1 dB and an associated gain (G/sub ass/) of 12 dB. To our knowledge, these results are the best f/sub t/, f/sub max/ and microwave noise performance ever reported on GaN HEMT grown on Silicon substrate.     

A dual-b and RF front-end of direct conversion receiver for wireless CDMA cellular phones with GPS capability

A highly integrated direct conversion receiver for cellular code division multiple access (CDMA) and GPS applications is successfully developed using a 0.5-/spl mu/m SiGe BiCMOS technology. The receiver consists of two low-noise amplifiers (LNAs), a dual-band mixer, two voltage-controlled oscillators (VCOs), a local-oscillator signal generation block, and channel filters. The CDMA LNA achieves a noise figure of 1.3 dB, an input-referred third-order intercept point (IIP3) of 10.9 dBm, and a gain of 15.3 dB with a current consumption of 9.8 mA in the high-gain mode. The mixer for the CDMA mode achieves an uncalibrated input-referred second-order intercept point of 53.7 dBm, an IIP3 of 6.4 dBm, a noise figure of 7.2 dB and a voltage gain of 37.2 dB. The phase noise of the CDMA VCO is approximately -133 dBc/Hz at a 900-kHz offset from a 1.762-GHz operating frequency. It exceeds all the CDMA requirements when tested on a handset.     

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-/spl mu/m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.     

A 4-/spl mu/a quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications

This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm/sup 2/ in 0.25-/spl mu/m CMOS. Very high efficiencies are achieved over a load range of 0.1-400 mA. Measured quiescent current in PFM mode is 4 /spl mu/A.