A modified MAP decoder architecture for low power consumption using folded technique

A modified MAP decoder architecture to reduce the power using folded technique is presented in this article. Firstly, the folded technique is applied in the interleaving and deinterleaving unit and then in the MAP decoder unit. The number of latches is reduced by using folded technique in the interleaving and deinterleaving unit. Here the end-to-end delay by using the proposed folded technique in the interleaving block is 2?M. But existing reports reveal that end-to-end delay is 2MN???2?M?+?2 for BI and M(N???1) for FCI. In addition to the end-to-end delay, the number of latches is also reduced by using folded technique. We have used only M???2 latches, whereas for other methods the number of latches utilised is more. The proposed MAP decoder reduce the memory elements up to 88% for the block interleaver, when M?=?NJ. In addition to that we achieved a memory element of 2 ^{K ?1?}+?4 when calculating LLR by applying folded technique in the MAP decoder. Total power consumption is 160.3mW when folded technique is used in the interleaving block and the MAP decoder section. This ratio is less than the existing reported values for K?=?5, code rate ½ and k?=?4.     

High-performance VLSI architectures for turbo decoders with QPP interleaver

This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW – SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of ‘mod’ operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.     

Novel construction of quasi-cyclic low-density parity-check codes with variable code rates for cloud data storage systems

This paper proposed a novel method for constructing quasi-cyclic low-density parity-check (QC-LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC-LDPC codes. Investigations revealed that the proposed large-sized QC-LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10⁻¹⁰ at 3.5 dB E_b/N₀ than conventional LDPC codes, which showed a BER of 10⁻⁷ at 3 dB E_b/N₀. Subsequently, implementation of the proposed QC-LDPC code in a software-defined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10⁻⁶ at 4.2 dB E_b/N₀ was achieved. Then, the performance of the proposed codes based on their encoding–decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed–Solomon codes.     

Improved Reliability‐Based Iterative Decoding of LDPC Codes Based on Dynamic Threshold

A serial concatenated decoding algorithm with dynamic threshold is proposed for low‐density parity‐check codes with short and medium code lengths. The proposed approach uses a dynamic threshold to select a decoding result from belief propagation decoding and order statistic decoding, which improves the performance of the decoder at a negligible cost. Simulation results show that, under a high SNR region, the proposed concatenated decoder performs better than a serial concatenated decoder without threshold with an E_b/N₀ gain of above 0.1 dB.     

A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS

A channel decoder chip compliant with the 3GPP mobile wireless standard is described. It supports both data and voice calls simultaneously in a unified turbo/Viterbi decoder architecture. For voice services, the decoder can process over 128 voice channels encoded with rate 1/2 or 1/3, constraint length 9 convolutional codes. For data services, the turbo decoder is capable of processing any mix of rate 1/3, constraint length 4 turbo encoded data streams with an aggregate data rate of up to 2.5 Mb/s with 10 iterations per block (or 4.1 Mb/s with six iterations). The turbo decoder uses the logMAP algorithm with a programmable logsum correction table. It features an interleaver address processor that computes the 3GPP interleaver addresses for all block sizes enabling it to quickly switch context to support different data services for several users. The decoder also contains the 3GPP first channel de-interleaving function and a post-decoder bit error rate estimation unit. The chip is fabricated in a 0.18-/spl mu/m six-layer metal CMOS technology, has an active area of 9 mm/sup 2/, and has a peak clock frequency of 110.8 MHz at 1.8 V (nominal). The power consumption is 306 mW when turbo decoding a 2-Mb/s data stream with ten iterations per block and eight voice calls simultaneously.     

Interleaver design for turbo codes

The performance of a turbo code with short block length depends critically on the interleaver design. There are two major criteria in the design of an interleaver: the distance spectrum of the code and the correlation between the information input data and the soft output of each decoder corresponding to its parity bits. This paper describes a new interleaver design for turbo codes with short block length based on these two criteria. A deterministic interleaver suitable for turbo codes is also described. Simulation results compare the new interleaver design to different existing interleavers     

基于无冲突多项式交织器的高速并行Turbo解码器

提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证.设计的Turbo并行高速解码器半次迭代的效率为6.9 bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法.该设计节约了计算电路和存储量.     

Performance of a turbo‐coded CDMA system in a mobile satellite channel

The bit error rate (BER) performance of a turbo‐coded code‐division multiple‐access (CDMA) system operating in a satellite channel is analysed and simulated. The system performance is compared for various constituent decoders, including maximum a posteriori probability (MAP) and Max‐Log‐MAP algorithms, and the soft‐output Viterbi algorithm. The simulation results indicate that the Max‐Log‐MAP algorithm is the most promising among these three algorithms in overall terms of performance and complexity. It is also shown that, for fixed code rate, the BER performance is improved substantially by increasing the number of iterations in the turbo decoder, or by increasing the interleaver length in the turbo encoder. The results in this paper are of interest in CDMA‐based satellite communications applications. Copyright © 2005 John Wiley & Sons, Ltd.     

Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders

Wireless communication standards make use of parallel turbo decoder for higher data rate at the cost of large hardware resources. This paper presents a memory-reduced back-trace technique, which is based on a new method of estimating backward-recursion factors, for the maximum a posteriori probability (MAP) decoding. Mathematical reformulations of branch-metric equations are performed to reduce the memory requirement of branch metrics for each trellis stage. Subsequently, an architecture of MAP decoder and its scheduling based on the proposed back trace as well as branch-metric reformulation are presented in this work. Comparative analysis of bit-error-rate (BER) performances in additive white Gaussian noise channel environment for MAP as well as parallel turbo decoders are carried out. It has shown that a MAP decoder with a code rate of 1/2 and a parallel turbo decoder with a code rate of 1/3 have achieved coding gains of 1.28 dB at a BER of 10\(^{-5}\) and of 0.4 dB at a BER of 10\(^{-4}\), respectively. In order to meet high-data-rate benchmarks of recently deployed wireless communication standards, very large scale integration implementations of parallel turbo decoder with 8–64 MAP decoders have been reported. Thereby, savings of hardware resources by such parallel turbo decoders based on the suggested memory-reduced techniques are accounted in terms of complementary metal oxide semiconductor transistor count. It has shown that the parallel turbo decoder with 32 and 64 MAP decoders has shown hardware savings of 34 and 44 % respectively.     

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high-throughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm² and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations     

Interfacial Polarization Restriction for Ultrahigh Energy-Storage Density in Lead-Free Ceramics

Dielectric capacitors with high power densities are crucial for pulsed electronic devices and clean energy technologies. However, their breakdown strengths (E_b) strongly limit their power densities. Herein, by modifying the interfacial polarization by adjusting the difference in activation energies (Δϕ) between the grain and grain boundary phases, the significant enhancement of E_b in the (1-x)(0.94Na_0.5Bi_0.5TiO₃-0.06BaTiO₃)-xCa_0.7La_0.2TiO₃ (NBT-BT-xCLT, x = 0, 0.18, 0.23, 0.28, 0.33, 0.38, and 0.43) ceramics is achieved. The results indicate that adding CLT introduces a super-paraelectric state, refines grain size, and, most importantly, decreases the Δϕ value. When Δϕ is tuned close to zero in the specific NBT-BT-0.38CLT sample, a significant boost in E_b value of 64 kV mm⁻¹ is obtained. As a result, the recoverable energy storage density of the ceramics reaches an unprecedented giant value of 15.1 J cm⁻³ together with a high efficiency of 82.4%, as well as ultrafast discharge rate of 32 ns, and high thermal and frequency stability. The results demonstrate that interfacial polarization engineering holds huge promise for the development of dielectrics with high-energy-storage performance.     

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbo-decoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm² area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm²/Mbps and energy efficiency of 0.55 nJ/b/iter.     

Π-Skeleton Tailoring of Olefin-Linked Covalent Organic Frameworks Achieving Low Exciton Binding Energy for Photo-Enhanced Uranium Extraction from Seawater

Adsorption-photocatalysis technology based on covalent organic frameworks (COFs) offers an alternative method for advancing the field of uranium extraction from seawater. When determining the photocatalytic activity of COFs, the binding energy of excitons (E_b) functions is the decisive factor. Nevertheless, the majority of reported COFs have a large E_b, which seriously restricts their application in the field of photocatalysis. Using a practical π-skeleton engineering strategy, the current study synthesizes three donor-acceptor olefin-linked COFs containing amidoxime units in an effort to minimize E_b. Theoretical and experimental results reveal that the construction of planar and continuous π-electron delocalization channels can significantly reduce E_b and promote the separation of electron-hole pairs, thereby enhancing the photocatalytic activities. Moreover, the E_b of the TTh-COF-AO with a planar π-skeleton donor is significantly reduced, and exhibits a substantially smaller E_b (38.4 meV). Under visible light irradiation, a high photo-enhanced uranium extraction capacity of 10.24 mg g⁻¹ is achieved from natural seawater without the addition of sacrificial reagents, which is superior to the majority of olefin-linked COFs that have been reported to date. This study, therefore, paves the way for the development of tailored, efficient COFs photocatalysts for the extraction of uranium from seawater.     

Multistage recursive interleaver for turbo codes in DS-CDMA mobileradio

A multistage recursive block interleaver (MIL) is proposed for the turbo code internal interleaver. Unlike conventional block interleavers, the MIL repeats permutations of rows and columns in a recursive manner until reaching the final interleaving length. The bit error rate (BER) and frame error rate (FER) performance with turbo coding and MIL under frequency-selective Rayleigh fading are evaluated by computer simulation for direct-sequence code-division multiple-access mobile radio. The performance of rate-1/3 turbo codes with MIL is compared with pseudorandom and S-random interleavers assuming a spreading chip rate of 4.096 Mcps and an information bit rate of 32 kbps. When the interleaving length is 3068 bits, turbo coding with MIL outperforms the pseudorandom interleaver by 0.4 dB at an average BER of 10^-6 on a fading channel using the ITU-R defined Vehicular-B power-delay profile with the maximum Doppler frequency of f_D = 80 Hz. The results also show that turbo coding with MIL provides superior performance to convolutional and Reed-Solomon concatenated coding; the gain over concatenated coding is as much as 0.6 dB     

Space diversity schemes with feedback for three transmit antennas

In this paper, we propose two-space diversity schemes with feedback for three transmit antennas which perform independently for each signaling interval. The first one is a pure code selection technique which provides, with two feedback bits, an E_b/N₀ advantage of nearly compared to the pure antenna selection technique where the best one of the three antennas is used. The second one is a hybrid selection scheme which consists of a combination of antenna and code selection techniques. The selection is performed out of 13 possible precoding vectors requiring four feedback bits, to maximize the diversity for all possible channel situations. It was shown by computer simulations that E_b/N₀ gains of approximately 1.25 and are possible, compared to the pure antenna selection and code selection schemes, respectively. Mapping rules between feedback codewords and precoding vectors, which results in improvement over random mapping, are obtained to minimize the error probability in the case of feedback errors.     

A coded 8-PSK system for 140 Mb/s information rate transmission over 80 MHz non-linear transponders

A combined 8-PSK modulation and rate 7/9 convolutional coding technique is proposed for 140 Mb/s information rate transmission over the 80 MHz INTELSAT transponders, thus achieving a bandwidth efficiency of 1.75 b/s/Hz of allocated bandwidth. The desired power efficiency is to achieve a bit error rate of 10^?6 at an E_b/N₀ of 11 dB, including modem and codec implementation losses. The proposed system employs an 8-PSK modem operating at a 60 MHz symbol rate (or 180 Mb/s bit rate), as well as a rate 7/9 convolutional encoder and a 16-state Viterbi algorithm decoder operating at 60 MHz. The rate 7/9 code is periodically time varying and is designed to maximize the Euclidean distance between the modulated codeword sequences, thereby achieving a 3 dB asymptotic coding gain relative to the conventional QPSK system over an AWGN channel. This code is also designed to reduce decoder complexity for high-speed operations. The performance of the proposed system over INTELSAT V and VI non-linear transponders was evaluated by Monte Carlo computer simulation. The 180 Mb/s 8 PSK modem, including the automatic frequency control, automatic gain control, carrier recovery and clock recovery circuits, has been implemented and tested. The complete Viterbi decoder is being implemented on five boards, and the critical add-compare-select (ACS) circuit of the high-speed Viterbi algorithm decoder is being implemented with hybrid technology employing 100-K series emitter-coupled logic dies on specially designed ceramic substrates. The ACS circuit operates at a speed exceeding 120 MHz, well over the design goal of 60 MHz. Construction of this codec is almost complete.     

Coding theorems for turbo code ensembles

This paper is devoted to a Shannon-theoretic study of turbo codes. We prove that ensembles of parallel and serial turbo codes are "good" in the following sense. For a turbo code ensemble defined by a fixed set of component codes (subject only to mild necessary restrictions), there exists a positive number γ₀ such that for any binary-input memoryless channel whose Bhattacharyya noise parameter is less than γ₀, the average maximum-likelihood (ML) decoder block error probability approaches zero, at least as fast as n ^-β, where β is the "interleaver gain" exponent defined by Benedetto et al. in 1996     

A Subthreshold PMOS Analog Cortex Decoder for the (8, 4, 4) Hamming Code

This paper presents a method for decoding high minimal distance (d_min) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher d_min than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high d_min, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof‐of‐concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25‐μm CMOS. It outperforms an equivalent LDPC‐like decoder by 1 dB at BER=10^?5 and is 44 percent smaller and consumes 28 percent less energy per decoded bit.     

Adaptive Selection of Parameters of S-Random Interleaver in Wireless Data Transmission Systems with Turbo Coding

The paper proposes an adaptive method for selecting the parameters of S-random interleaver of turbo-code codex in wireless data transmission systems under conditions of a priori uncertainty for enhancing the reliability of data transmission and reducing the computational complexity of the coding/decoding process of turbo codes. This method is based on the adaptive selection of parameters of S-random interleaver depending on values of the normalized quantity of sign reversals of a posteriori-a priori log-likelihood function ratios (LLFR) regarding the transmitted data bits of turbo-code decoder. The results of simulation modeling show that the rational parameters of S separation of data bit interleaving for S-random interleaver are obtained depending on the values of signal-to-noise ratio in channel and the normalized number of sign reversals of a posteriori-a priori LLFR of interactive turbo-code decoder. As a result, the energy gain of coding can be obtained, the complexity of its hardware and software implementation can be reduced, and reliability of data transmission can be enhanced as compared to the known results, for example, the fourth generation mobile communication system 4G LTE-Advanced.     

Design of a transport triggered vector processor for turbo decoding

In order to meet the requirement of high data rates for next generation wireless systems, efficient implementations of receiver algorithms are essential. On the other hand, faster time-to-market motivates the investigation of programmable implementations. This paper presents a novel design of a programmable turbo decoder as an application-specific instruction-set processor (ASIP) using transport triggered architecture (TTA). The processor architecture is designed in such a manner that it can be programmed with high level language to support different suboptimal maximum a posteriori (MAP) algorithms in a single TTA processor. The design enables the designer to change the algorithms according to the frame error rate performance requirement. A quadratic polynomial permutation interleaver is used for contention-free memory access and to make the processor 3GPP LTE compliant. Several optimization techniques to enable real time processing on programmable platforms are introduced. The essential parts of the turbo decoding algorithm are designed with vector function units. Unlike most other turbo decoder ASIPs, high level language is used to program the processor to meet the time-to-market requirements. With a single iteration, 68.35 Mbps decoding speed is achieved for the max-log-MAP algorithm at a clock frequency of 210 MHz on 90 nm technology.