Extrapolated fmax of heterojunction bipolar transistors

It is shown that the extrapolated f_max of heterojunction bipolar transistors (HBT's) can be written in the form f _max=√f_T/8π(RC)_eff, where f_T is the common-emitter, unity-current-gain frequency, and where (RC)_eff is a general time constant that includes not only the effects of the base resistance and collector-base junction capacitance, but also the effects of the parasitic emitter and collector resistances, and the dynamic resistance 1/g_m, where g_m is the transconductance. Simple expressions are derived for (RC) _eff, and these are applied to two state-of-the-art devices recently reported in the literature. It is demonstrated that, in modern HBT's, (RC)_eff can differ significantly from the effective base-resistance-collector-capacitance product conventionally assumed to determine f_max     

Ultrahigh fT and fmax new self-alignmentInP/InGaAs HBT's with a highly Be-doped base layer grown by ALE/MOCVD

We report on a new self-alignment (SA) process and microwave performance of ALE/MOCVD grown InP/InGaAs heterojunction bipolar transistors (HBT's) with a base doping concentration of 1×10² 0 cm^-3. We obtained f_T of 161 GHz and f_max of 167 GHz with a 2×10 μm emitter. These high values indicate the best performance of InP/InGaAs HBT's ever reported, in so far as we know. These values were attained by reducing the base resistance using ALE/MOCVD and base-collector capacitance using a new SA process. These results indicate the great potential of these devices for ultrahigh-speed application     

Process investigations for a 30-GHz fT submicrometerdouble poly-Si bipolar technology

Major process issues are investigated to establish a manufacturable process for a 30-GHz f_T deep-trench isolated submicrometer double polysilicon bipolar technology. A thinner deep-trench surface oxide minimizes crystal defects generated by thermal stresses during the subsequent processes, and significantly improves collector-to-emitter leakage currents in npn transistors. The effects of reactive-ion-etch (RIE) process used for the base surface oxide etch are evaluated in terms of current gain, emitter resistance, and cutoff frequency of the npn transistors. Silicon surface roughness created by an RIE process produces a nonuniform interface oxide film between the emitter polysilicon and the silicon surface, which results in a lower current gain due to a retardation of arsenic diffusion from the emitter polysilicon through the unbroken thicker portion of the interface oxide film. Lateral pnp transistors and Schottky diodes using a vanadium silicide are characterized as a function of epitaxial layer thickness. Schottky diodes are integrated with high performance npn transistors without using extra photo-masking process steps. The reverse leakage currents of Schottky diodes fabricated by using an RIE process are acceptable for practical use in circuits. A planarization process is investigated by employing an RTA reflow of BPSG films deposited in an LPCVD furnace. The maximum RTA reflow temperature is limited to 1000°C in order to maintain an acceptable integrity of TiSi₂ layer formed on top of the n+ polysilicon layer. The planarity achieved by an RTA reflow at a temperature between 975°C and 1000°C is acceptable for double polysilicon bipolar integrated circuits using metal interconnects produced by an electroplated gold process     

GaInP/GaAs double heterojunction bipolar transistor with highfT, fmax, and breakdown voltage

We report on the dc and microwave performance of an MOCVD-grown carbon-doped GaInP/GaAs double heterojunction bipolar transistor (DHBT) with a thin highly doped n-type GaInP layer in the collector. The DHBT showed improved current-voltage characteristics at low collector-emitter bias compared with those of a DHBT without the heavily doped GaInP layer, while maintaining a high breakdown voltage (BV_CEO~20 V). Small area, self-aligned emitter transistors with two 2×5 μm² emitter fingers were fabricated and exhibited f_T and f_max of 53 GHz and 75 GHz, respectively. These results indicate the promise of carbon-doped base GaInP/GaAs DHBT's for high-power microwave applications     

An analytic expression of fmax for HBTs

An analytic expression of f_max is derived based on a practical HBT circuit model where collector junction capacitance is split up into internal and external parts. It shows that for advanced HBTs, f_max is well characterized by the product of the base resistance and internal collector capacitance. In other words, the external collector capacitance has only a small impact on the determination of f_max. Good agreement between experimental results and numerical circuit simulation confirms the validity of the HBT circuit model. The influence of the external collector capacitance on maximum available gain is also described     

AlGaN/GaN HEMTs on silicon substrates with fT of 32/20GHz and fmax of 27/22 GHz for 0.5/0.7 μm gate length

AlGaN/GaN HEMTs on silicon substrates have been realised and their static and small signal characteristics investigated. The AlGaN/GaN (x=0.23) material structures were grown on (111) p-Si by LP-MOVPE. Devices exhibit a saturation current density of 0.53 to 0.68 A/mm and a peak extrinsic transconductance of 110 mS/mm. A unity gain frequency of 20 and 32 GHz and a maximum frequency of oscillation of 22 and 27 GHz are obtained for devices with a gate length of 0.7 and 0.5 μm, respectively. These values are the highest reported so far on AlGaN/GaN/Si HEMTs and are comparable to those known for devices using sapphire and SiC substrates     

High fmax InP double heterojunction bipolar transistorswith chirped InGaAs/InP superlattice base-collector junction grown byCBE

We report the performance of InP Double Heterojunction Bipolar Transistors (DHBT's) with a chirped InGaAs/InP superlattice B-C junction grown by CBE. The B-C junction of the DHBT was graded with a 10-period InGaAs/InP chirped superlattice (CSL) between the InGaAs base and the lightly doped InP collector. A highly doped thin layer was also included at the end of the CSL to offset the quasi-electric field arising from the grade and suppress further the carrier blocking effect across the B-C heterojunction. The InP/InGaAs CSL DHBT demonstrated a high BV_CEO of 18.3 V with a typical current gain of 55 with minimal carrier blocking up to high current densities. Maximum cutoff frequencies of f_max=146 GHz and f_r=71 GHz were obtained from the fabricated 2×10 μm²-emitter DHBT     

High breakdown voltage InGaAs/InP double heterojunction bipolar transistors with fmax=256 GHz and BVCEO= 8.3 V

正An InGaAs/InP DHBT with an InGaAsP composite collector is designed and fabricated using triple mesa structural and planarization technology.All processes are on 3-inch wafers.The DHBT with an emitter area of 1 x 15μm~2 exhibits a current cutoff frequency f_t = 170 GHz and a maximum oscillation frequency f_(max) = 256 GHz.The breakdown voltage is 8.3 V,which is to our knowledge the highest BV_(CEO) ever reported for InGaAs/InP DHBTs in China with comparable high frequency performances.The high speed InGaAs/InP DHBTs with high breakdown voltage are promising for voltage-controlled oscillator and mixer applications at W band or even higher frequencies.     

Small-sized collector-up Ge/GaAs heterojunction bipolar transistorswith high gain, low base resistance, and high fmax

Small-sized collector-up Ge/GaAs HBT's are successfully fabricated and their operation at a high collector current density and at a high frequency is realized for the first time. The current gain of these devices reaches a peak value as large as 200 at a current density 6×10⁴ Acm^-2, and no degradation in the current gain is observed as the collector width is decreased down to 2 μm. The capability of lower voltage operation is also shown. Intrinsic and extrinsic base resistances are as low as 180 Ω/□ and 90 Ω/□, respectively. The calibrated values of f_T and f_max are 25 GHz and 60 GHz, respectively. The larger value of f_max compared with f_T might be attributed to low base resistance and low base-collector capacitance as expected from the collector-up structure     

A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz fT silicon bipolar technology

Clock and data recovery (CDR) circuits are key electronic components in future optical broadband communication systems. In this paper, we present a 40-Gb/s integrated CDR circuit applying a phase-locked loop technique. The IC has been fabricated in a 50-GHz f _T self-aligned double-polysilicon bipolar technology using only production-like process steps. The achieved data rate is a record value for silicon and comparable with the best results for this type of circuit realized in SiGe and III-V technologies     

Lattice-Matched InP-Based HEMTs with fT of 120GHz

Lattice-matched InP-based InAlAs/InGaAs HEMTs with 120GHz cutoff frequency are reported.These devices demonstrate excellent DC characteristics:the extrinsic transconductance of 600mS/mm,the threshold voltage of －1.2V,and the maximum current density of 500mA/mm.     

0.9 V rail-to-rail constant gm CMOS amplifier input stage

Presented is a 0.9 V rail-to-rail constant g_m CMOS amplifier input stage consisting of complementary differential pairs and a g_m control circuit. The g_m control circuit eliminates the g_m dead zone, which occurs in the conventional rail-to-rail amplifier with ultra-low supply voltages. The proposed amplifier input stage has a constant g_m that varies by ±2.3% for rail-to-rail input common-mode levels. To verify the proposed amplifier design, an experimental prototype operational amplifier is also implemented using 0.35 mm standard CMOS technology.     

0.10 μm graded InGaAs channel InP HEMT with 305 GHzfT and 340 GHz fmax

We report here 305 GHz f_T, 340 GHz f_max, and 1550 mS/mm extrinsic g_m from a 0.10 μm In_xGa _1-xAs/In_0.62Al_0.48As/InP HEMT with x graded from 0.60 to 0.80. This device has the highest f_T yet reported for a 0.10 μm gate length and the highest combination of f _T and f_max reported for any three-terminal device. This performance is achieved by using a graded-channel design which simultaneously increases the effective indium composition of the channel while optimizing channel thickness     

Direct ion-implanted 0.12 μm GaAs MESFET with ft of121 GHz and fmax of 160 GHz

An 0.12 μm gate length direct ion-implanted GaAs MESFET exhibiting excellent DC and microwave characteristics has been developed. By using a shallow implant schedule to form a highly-doped channel and an AsH₃ overpressure annealing system to optimize the shallow dopant profile, the GaAs MESFET performance was further improved. Peak transconductance of 500 mS/mm was obtained at I_ds =380 mA/mm. A noise figure of 0.9 dB with associated gain of 8.9 dB were achieved at 18 GHz. The current gain cutoff frequency f_max of 160 GHz indicates the suitability of this 0.12 μm T-gate device for millimeter-wave IC applications     

50-nm T-Gate InAlAs/InGaAs Metamorphic HEMTs With Low Noise and High fT Characteristics

We report 50-nm T-gate metamorphic high-electron mobility transistors (MHEMTs) with low noise figure and high characteristics. The 30 mumtimes2 MHEMT shows a drain current density of 690 mA/mm, a g_m,max of 1270 mS/mm, an f_T of 489 GHz, and an of 422 GHz. In the frequency range of 59-61 GHz, the noise figure is less than 0.7 dB, and the associated gain was greater than 9 dB at a drain voltage of 1.3 V and a gate voltage of -0.8 V. To our knowledge, the MHEMT shows the best performance in terms of and noise figure among GaAs-based HEMTs.     

Interferometric measurement of the linewidth enhancement factor ofa 1.55-μm strained multiquantum-well InGaAs/InGaAsP amplifier

The linewidth enhancement factor of an InGaAs/InGaAsP strained multiquantum well optical amplifier was measured interferometrically. It varied from 3 to 18 over the wavelength range from 1500 to 1600 nm with injection currents varying from one to four times the lasing threshold of the uncoated device. A rate equation model gave differential gain and refractive index change per carrier, respectively, in the range 0.3 to 2.5×10^-15 cm² and -5 to -8×10^-20 cm³     

InGaP/GaAs heterojunction bipolar transistor and RF power amplifier reliability

Electrothermal stress on advanced InGaP/GaAs heterojunction bipolar transistors (HBTs) was carried out experimentally. It showed a long-term stress-induced base current instability and a decrease in the DC current gain. A class-AB RF power amplifier (PA) was also considered to study the stress effect on the amplifier’s RF performance. The SPICE Gummel–Poon (SGP) model parameters were extracted from the pre- and post-stress HBT data and used in Cadence SpectreRF simulation. The amplifier’s post-stress RF characteristics, such as the output power and power-added efficiency (PAE), remained almost unchanged even though the post-stress HBT’s DC current gain had dropped to 73.6% of its initial value.     

A 0.2-μm self-aligned selective-epitaxial-growth SiGe HBTfeaturing 107-GHz fmax and 6.7-ps ECL

A 0.2-μm self-aligned selective-epitaxial-growth (SEG) SiGe heterojunction bipolar transistor (HBT), with shallow-trench and dual-deep-trench isolations and Ti-salicide electrodes, has been developed. The 0.6-μm-wide Si-cap/SiGe-base multilayer was selectively grown by UHV/CVD. The process, except the SEG, is almost completely compatible with well-established bipolar-CMOS technology and the SiGe HBTs were fabricated on a 200-mm wafer line. The SiGe HBTs have demonstrated a peak cutoff frequency of 90 GHz, a peak maximum oscillation frequency of 107 GHz, and an ECL gate delay time of 6.7 ps. Four-level interconnects, including MIM capacitors and high-Q inductors, were formed by chemical mechanical polishing     

Enhancement of fmax in InP/InGaAs HBTs by selectiveMOCVD growth of heavily-doped extrinsic base regions

InP/InGaAs heterojunction bipolar transistors (HBT's) with selectively grown heavily-doped extrinsic base layers have been fabricated. A new selective metalorganic chemical vapor deposition (MOCVD) method using a very high-speed rotating susceptor, which can attain high selectivity even at low growth temperature, is employed for the extrinsic-base regrowth. The maximum f_max of the HBT with the selectively grown extrinsic-base layer is 141 GHz, which is more than 50% larger than that of a HBT without the selective growth. The base resistances are estimated by a small-signal equivalent-circuit analysis and transmission line model measurements, and we find that the resistance is reduced to be about a half by the selective regrowth. This significant reduction is achieved by the decrease of base contact resistance as well as the low regrowth-interface resistance. We also discuss Zn redistribution during the extrinsic base regrowth     

A 60-GHz fT super self-aligned selectively grownSiGe-base (SSSB) bipolar transistor with trench isolation fabricated onSOI substrate and its application to 20-Gb/s optical transmitterICs

A 60-GHz cutoff frequency (f_T) super self-aligned selectively grown SiGe-base (SSSB) bipolar technology is developed. It is applied to 20-Gb/s optical fiber transmitter ICs. Self-aligned bipolar transistors mutually isolated by using a BPSG-filled trench were fabricated on a bond-and-etchback silicon-on-insulator (SOI) substrate to reduce the collector-substrate capacitance C_CS. The SiGe base was prepared by selective epitaxial growth (SEG) technology. A 0.4-μm wide emitter was used to reduce the junction capacitances. The maximum cutoff frequency f_T and the maximum frequency of oscillation f_max were 60 and 51 GHz, respectively. By using this technology, Si-ICs for an optical transmitter system were made, such as a selector (a multiplexer without input and output retiming D-type flip-flops (D-F/Fs)), a multiplier, and a D-F/F. An internal high-speed clock buffer circuit achieves stable operation under a single clock input condition in the selector and the multiplier ICs. Their stable operation was confirmed up to 20 Gb/s. The selector IC for data multiplexing operates at over 30 Gb/s