Highly reliable, high-C DRAM storage capacitors with CVD TA2O5 films on rugged polysilicon

The authors report on a highly reliable stacked storage capacitor with ultrahigh capacitance using rapid-thermal-annealed low-pressure chemical vapor deposited (LPCVD) Ta₂O₅ films (~100 Å) deposited on NH₃-nitrided rugged poly-Si electrodes. Capacitances as high as 20.4 fF/μ² (corresponding to the thinnest t_ox.eff (16.9 Å) ever reported using LPCVD-Ta₂O₅ and poly-Si technologies) have been achieved with excellent leakage current and time-dependent dielectric breakdown (TDDB) characteristics. Extensive electrical characterization over a wide temperature range (~25-300°C) shows that Ta₂O ₅ films on rugged poly-Si electrodes have a better temperature stability in dielectric leakage and breakdown compared to the films on smooth poly-Si electrodes     

Oxidized Ta2O5/Si3N4dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta₂O₅/Si₃ N₄ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta₂O₅/Si₃N₄ layers was performed at temperatures higher than 900°C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ μm², which is equivalent to that of a 6.0- to 6.5-nm-thick SiO₂. The leakage current at an effective electric field of 5 MV/cm is less than 10^-9 A/cm². Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

Trends in DRAM dielectrics

We trace the development of the ON/ONO dielectric film and examine the potential of new dielectrics with high dielectric constants such as Ta₂O₅ and ferroelectric materials. We also examine hemispherical grained (HSG) polysilicon, which is an innovative way to increase the effective area of the capacitor     

Two-step annealing technique for leakage current reduction inchemical-vapor-deposited Ta2O5 film

A capacitor technology developed to obtain extremely thin Ta₂ O₅ dielectric film with an effective SiO₂ film thickness down to 3 nm (equivalent to 11 fF/μm²) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta₂ O₅ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O₃) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O₂) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps     

Low-resistance bandgap-engineeredW/Si1-xGex/Si contacts

Bandgap-engineered W/Si_1-xGe_x/Si junctions (p⁺ and n⁺) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si_0.7Ge _0.3 layer which is implanted and annealed using RTA. The Si _1-xGe_x layer can then be selectively thinned using NH₄OH/H₂O₂/H₂O at 75°C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6×10^-9 A/cm² (areal), 7.45×10^-12 A/cm (peripheral) for p⁺/n and 3.5×10^-10 A/cm² (peripheral) for n⁺/p. W contacts were formed using selective LPCVD on Si_1-xGe_x. A specific contact resistivity of better than 3.2×10^-8 Ω cm² for p ⁺/n and 2.2×10^-8 Ω cm² for n⁺/p is demonstrated-an order of magnitude n⁺ better than current TiSi₂ technology. W/Si_1-xGe _x/Si junctions show great potential for ULSI applications     

Design optimization of stacked layer dielectrics for minimum gate leakage currents

An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I–V curves are observed for Si₃N₄/SiO₂, Ta₂O₅/SiO₂, Ta₂O₅/SiO_2−yN_y, Ta₂O₅/Si₃N₄, and TiO₂/SiO₂ stacked gates except for Al₂O₃/SiO₂ structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated.     

Development of Embedded Three-Dimensional 35-nF/mm2 MIM Capacitor and BiCMOS Circuits Characterization

This paper summarizes the electrical characterization of MIM capacitor realized in three dimensions. Manufacturing of the device is described, as well as an electrical comparison of three dielectrics, Si₃N₄, Al₂O₃, Ta₂O₅ and two deposition methods, metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). Selecting Al₂O₃ deposited by ALD, high density of 35 nF/mm² is obtained with low leakage current. Statistical measurements put forward the industrial robustness of the device integrated in BiCMOS technology. Three circuits embedding this new device are characterized: a high-pass filter, a voltage-controlled oscillator (VCO), and a phase-locked loop (PLL). They demonstrate excellent performances with significant area and assembly costs savings.     

Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics

Capacitors with ultra-thin (6.0-12.0 nm) CVD Ta₂O₅ film were fabricated on lightly doped Si substrates and their leakage current (I_g-V_g) and capacitance (C-V) characteristics were studied. For the first time, samples with stack equivalent oxide thickness around 2.0 nm were compared with ultra-thin silicon dioxide and silicon oxynitride. The Ta₂O₅ samples showed remarkably lower leakage current, which not only verified the advantages of ultra-thin Ta₂O₅ as dielectrics for high density DRAM's, but also suggested the possibility of its application as the gate dielectric material in MOSFET's     

Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

Plasma-charging effects on submicron MOS devices

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si₃N₄ and Ta₂O₅ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si₃N₄ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta₂O₅ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta₂O₅ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta₂O₅ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation     

Reduction of current leakage in chemical-vapor deposited Ta2O5 thin-films by oxygen-radical annealing [DRAMdielectric]

The electrical properties of CVD-Ta₂O₅ thin-films are improved by post-deposition oxygen-radical annealing. Since this annealing is carried out at very low pressure (10^-6 torr), the growth of SiO₂ in Ta₂O ₅/Si interface is small, and the residual carbon in the film is reduced. The damage to the Ta₂O₅ film caused by oxygen ion bombardment is negligible, because few charged particles reach the film. A critical voltage V_crit of 1.45 V for the leakage current less than 10^-8 A/cm² was realized by these Ta₂O₅ films with the effective thickness t_eff of 2.59 nm. The V_crit value for oxygen-radical annealing is higher than that for oxygen-plasma annealing     

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3-μm electron-beam lithography. This memory cell has an area of 1.28 μm². The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 μm, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 μm² because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta₂O₅ film equivalent to a 2.8-nm SiO₂ film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation     

Leakage current reduction in chemical-vapor-depositedTa2O5 films by rapid thermal annealing in N2O

This study aims to improve the electrical characteristics and reliability of low-pressure chemical vapor deposited (LPCVD) Ta₂ O₅, films by developing a new post-deposition single-step annealing technique. Experimental results indicate that excited oxygen atoms generated by N₂O decomposition can effectively repair the oxygen vacancies in the as-deposited CVD Ta₂ O₅ film, thereby resulting in a remarkable reduction of the film's leakage current. Two other post-deposition annealing conditions are compared: rapid thermal O₂ annealing and furnace dry-O₂ annealing. The comparison reveals that RTN₂O annealing has the lowest leakage current, superior thermal stability of electrical characteristics and the best time-dependent dielectric breakdown (TDDB) reliability     

Plasma charging damage on MOS devices with gate insulator ofhigh-dielectric constant material

Plasma charging effects on the gate insulator of high-dielectric constant (k) material in MOS devices deserve to be investigated because of different trap-assisted conduction mechanisms. Plasma-induced degradation in gate-leakage current and time to breakdown is clearly observed in this work. MOS device with Si₃N₄ film seems to have smaller degradation of gate-leakage current while it suffers shorter time to breakdown as compared to Ta₂O₅ samples. For devices with Ta₂O₅ film, a larger physical thickness suffers more reliability degradation from plasma charging damage because of the richer traps. Thus, a smaller physical thickness of high-k dielectric film is favorable for sub-micron MOS devices of ULSI application     

Roughness of ZnS:Pr,Ce/Ta2O5 interface andits effects on electrical performance of alternating current thin-filmelectroluminescent devices

Roughness effects of neighboring dielectrics on electrical characteristics of thin-film electroluminescent devices were investigated in order to improve the understanding of physics for the devices. Atomic force microscopy analysis reveal that thicker bottom layer of Ta₂O₅ shows rougher surface resulting in the rougher surface of ZnS:Pr,Ce layer. It can be easily seen that the dc leakage current increases rapidly with increase of surface roughness. Furthermore, it is notable that the initiation field of Poole-Frenkel current conduction is lowered by increasing surface roughness of Ta₂O₅ thin film. Internal charge-phosphor field (Q _int-F_p) analysis and capacitance-ac voltage (C-V) analysis for ITO-Ta₂O₅-ZnS:Pr,Ce-Al and ITO-Ta₂O₅-ZnS:Pr,Ce-Ta₂O₅-Al show that the steady state phosphor field is smaller and C-V curve in transition region is less steep with increase of root-mean-square roughness between lower dielectric and phosphor layer in the alternating current thin-film electroluminescent (ACTFEL) devices. Therefore, we conclude that interface roughness is one of the physical factors to change the electrical performance of ACTFEL device     

The observation of negative transconductance effect caused byreal-space-transfer of electrons in metal oxide semiconductor fieldeffect transistors fabricated with Ta2O5 gatedielectric

N-channel metal oxide semiconductor field effect transistors (MOSFETs) with Ta₂O₅ gate dielectric were fabricated. An intrinsic Ta₂O₅/silicon barrier height of 0.51 eV was extracted from the gate current. The effective Ta ₂O₅/silicon barrier height including image force barrier lowering is about 0.37 eV with drain to source voltage V_DS ranging from 1.5 V to 4.0 V. Due to the low barrier height, negative transconductance effect was observed in the linear region. The decrease of drain current is due to the real space transfer of electrons from the drain terminal to the gate electrode     

Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂      

The degradation of TDDB characteristics of Si02/Si3N4/Si02 stacked films caused by surfaceroughness of Si3N4 films [DRAMs]

The effect of surface roughness of Si₃N₄ films on time-dependent dielectric breakdown (TDDB) characteristics of SiO₂/Si₃N₄/SiO₂ (ONO) stacked films was investigated. The surface roughness of Si₃N ₄ films-was found to become higher with increasing deposition temperature and to cause the degradation of TDDB characteristics of ONO films in DRAMs. A local thinning of ONO films, evaluated from the TDDB characteristics, agreed with the surface roughness measured by atomic force microscopy (AFM) and cross-sectional transmission electron microscopy (XTEM). Dependence of time to breakdown of ONO films on the deposition conditions was interpreted by electric field intensification due to the surface roughness of Si₃N₄ films     

Dual Process Dielectric Formation for Decoupling Capacitors on Flexible Substrates

Large area, high density integrated capacitors within printed wiring boards can provide a substantial decoupling capacitance with very low parasitic inductance. Tantalum pentoxide (Ta₂O₅) is an excellent dielectric for this application due to the relatively high dielectric constant (~ 22-24), however the difficulty of fabricating large, defect-free capacitors has thus far prevented the realization of practical applications. This work demonstrates high performance capacitors with Ta₂O₅ dielectric developed with a two step oxidation scheme consisting of reactive sputtering followed by anodization. Thin films of Ta₂O₅ were deposited by reactive sputtering on silicon and also on Upilex^reg covered glass wafers using dc magnetron sputtering with a gas flow ratio of 10/90 O₂/Ar. In the two-step oxidation scheme, anodization is performed after reactively sputtering tantalum oxide films to obtain a densifled oxide structure. The electrical and physical properties of these two step sputtered/ anodized tantalum oxide films are shown to be superior to those of tantalum oxide films prepared by either anodization or sputtering alone. This work has shown that Ta₂O₅ is a potential dielectric for integrated capacitors that could be used in advanced packaging applications.