Three-Dimensional System-in-Package Using Stacked Silicon Platform Technology

In this paper, a novel method of fabricating three–dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.     

Life prediction methodology of system-in-package based on physics of failure

With the dramatic development of microelectronics technology, System-in-Package (SiP) becomes a brand-new direction for the More than Moore's law. In order to satisfy the demand of small-size, multi-function and high-performance, complex structures and variable materials are applied in SiPs, which introduce many reliability problems. To implement reliability qualification and health assessment, a life prediction methodology of SiP based on physics-of-failure (PoF) is studied in conjunction with simplified life cycle profile. In this paper, typical structures of SiPs, such as dies, components, interconnects are evaluated. And related PoF mechanisms, such as time dependent dielectric breakdown, electro-migration, die attach fatigue, thermal cyclic fatigue and etc., are considered. The inputs of the methodology contain hardware information and lifecycle profile. The hardware information of SiPs includes materials types and structures size. Lifecycle profile provides environmental conditions that the SiPs should experience. Based on these inputs, thermal distributions and stress-strain distributions of the SiP are analyzed by finite element analysis (FEA) tools. With the utilization of PoF models, lifetime matrix of the SiP is obtained. The output of the methodology is the lifetime matrix to predict lifetime of the SiP. Finally, a case study is done to guide engineering applications.     

Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application

This paper is for process development of assembly technologies used to fabricate the 3-D silicon carrier system-in–package (SiP). The five assembly technologies are wafer thinning, thin flip chip attach on silicon carrier, ultra low loop wire bonding, glass cap fabrication and sealing, and silicon carrier stacking. The developed SiP has three silicon carriers with four flip chip and one wire bond die chip attached to them and the carrier is stacked one above the other to form the 3-D silicon carrier SiP. Eight-inch bumped wafer thinning down to less than 100 $mu{hbox {m}}$, lower flip chip interconnect height between the chip and the carrier down to 35 $mu{hbox {m}}$, 40–50- $mu{hbox {m}}$ low loop wire bonding on overhang by direct reverse wire bonding method using 1-mil-diameter Au wire are achieved. And investigation of three types of thin film metallization systems for wirebonding and investigation of two different methods in fabricating glass cap are also studied.      

一种基于SiP技术的加速度计有源磁悬浮控制电路

加速度计是以加速度的观点来测量物体运动的传感器,它通过检测质量块的惯性力来测量载体的线加速度或角加速度。文中介绍的有源磁悬浮控制电路与陀螺浮子构成磁悬浮摆式积分陀螺加速度计,该加速度计具有量程大、测量精度高等优点。受整机系统内部装配空间的限制,在电路集成化产品的设计中,采用系统集成封装(SiP)技术设计与制作有源磁悬浮控制电路,减小电路产品的底面积和高度,适应整机系统对产品的装配和使用要求。同时详细介绍了基于SiP技术的电路设计方法,对HTCC工艺的SiP结构设计进行了阐述,并简述了HTCC工艺的SiP产品达到的技术性能和应用情况。     

基于SIP的VOIP系统合法侦听

基于SIP的VOIP属于分布式结构。在提出的模型中,侦听数据的获取涉及到SIP代理服务器和网关。在SIP代理服务器上获取信令数据,从网关上得到通信内容。所以,基于SIP的VOIP系统侦听的实现还涉及到代理服务器和网关的协调工作。     

基于系统级封装(SiP)的信息安全芯片集成设计

为了解决信息安全系统中,逻辑运算芯片与存储器难以实现集成的问题,并更充分地满足信息安全系统高性能、低功耗、高可靠性的要求,本文提出了"基于SiP的信息安全芯片集成"的概念及具体设计方案.根据此方案设计实现了一款集成CPU、Flash存储器、密码算法芯片的小型信息安全系统的SiP成品实例,该成品的功能和性能验证结果均满足系统的目标需求,从而证实了该设计方案的可行性.该方案也符合今后电子技术和信息安全系统的主要发展方向.     

系统级封装(SiP)技术研究现状与发展趋势

系统级封装(System in Package,SiP)已经成为重要的先进封装和系统集成技术,是未来电子产品小型化和多功能化的重要技术路线,在微电子和电子制造领域具有广阔的应用市场和发展前景,发展也极为迅速。对目前SiP技术的研究现状和发展趋势进行了综述,重点关注了国际上半导体产业和重要的研究机构在SiP技术领域的研究和开发,对我国SiP技术的发展做了简单的回顾和展望。     

Intra- and inter-temperature measurement BIST for SiP module using digital frequency analyser circuit

A method and a novel circuitry for intra- and inter-chip temperature measurement in a system in a package (SiP) module is presented. The proposed built-in self-test (BiST) system for the SiP module features a newly proposed digital frequency analyser (DFA) that can be used to efficiently discern clock period differences of up to 1 ns. The full digital interface of the DFA enables power and area efficient temperature measurements in an SiP.     

Sequential environmental stresses tests qualification for automotive components

The purpose is to create a new qualification methodology for plastic encapsulated electronic components used in an automotive environment at high temperature. It is based on the acceleration of failure mechanisms like ball bond lift (due to intermetallic Au–Al thickness growth), by combination of environmental stresses. The delamination measurement was used as an indicator of potential assembly weaknesses. An optimized package sequential qualification test flow is proposed.     

集成两路射频SiP发射器的设计和研究

随着移动通信和其它电子应用领域的不断进步,系统集成需求日益紧迫。除了可以应对系统性能、功能、成本和小型化的更高要求,系统级封装(SiP)在降低开发成本、实施灵活设计、缩短开发周期,和集成异质芯片上也有突出优势。这篇文章介绍了一个可用于手机基站系统的双通路发射系统SiP模块的开发。我们用计算模拟方法辅助优化设计,并成功制造和验证了SiP模块。SiP为内嵌电磁干扰屏蔽罩的12mmx12mmx1.9mm的多层栅格阵列封装(LGA)。各种射频信号性能均通过测试,包括严格的隔离度要求。电磁屏蔽测试和计算模拟结果高度吻合。最后,文章介绍了一种高效的计算模拟方法,极大地缩短了计算模拟的时间,并对未来射频SiP开发将提供有力帮助。     

Characterization and modelling of ageing failures on power MOSFET devices

A method based on the failure analysis of power MOSFET devices tested under extreme electrothermal fatigue is proposed. Failure modes are associated to several structural changes that have been investigated through acoustic, electron and ion microscopy. The main aging mode is related to the exponential increase in drain resistance due to delamination at the die attach. Earlier failures are observed when very local defects due to electrical over stresses (EOS) occur at the source metallization or at the wire bonding. Aging models were elaborated to account for the die attach delamination, but are still lacking to take in account the structural evolution of the Al metallization. This new methodology, based on accelerated tests and structural observations aims at designing a new generation of power components that will be more reliable.     

几种新的封装工艺

文章介绍了几种新的封装工艺,如新型圆片级封装工艺——OSmium圆片级封装工艺,它能够把裸片面积减少一半;新型SiP封装工艺——Smafti封装工艺,它改进了传统SiP封装工艺,把传输速度提高了10倍;超薄型封装工艺,超薄型变容二极管和Wi-Fi系统功率放大器;CDFN封装工艺和RCP封装工艺等。     

一种用于胎压传感器的新型系统级封装技术

TPMS IC是TPMS系统模块的关键核心器件,需要采用系统级封装(SiP)技术。对TPMS IC的一种新型SiP封装技术作了研究分析。在引线框架上引入电路板中介层,改善了芯片间电气互连与分布,增大了引入薄膜电阻电容元件的设计弹性。采用预成型模制部分芯片的封装技术,满足了IC与MEMS芯片不同的封装要求,还增强了SiP产品的可测试性和故障可分析性。采用敞口模封、灌装低应力弹性凝胶和传感器校准测试相结合的方法有效避免封装应力对MEMS压力传感器的影响。     

Signal Integrity Flow for System-in-Package and Package-on-Package Devices

As data rates required for systems in package (SiPs) increase and their complexity increases, signal integrity issues become increasingly difficult to address. The design flow of the SiP should therefore take into account these issues from the beginning. A design flow aimed at designing the SiP tracks is presented; its suitability for the design of packages comprising multiple stacked memories is verified through a design example. The proposed flow for signal integrity can be integrated easily within the complete design of the SiP.      

射频系统封装的发展现状和影响

电子产品小型化将进一步依赖微电子封装技术的进步.SiP（系统封装）所强调的是将一个尽可能完整的电子系统或子系统高密度地集成于单个封装体内,随着其技术的研究不断深入,封装规模不断扩大,其作用不断提升,它在射频领域中的应用特性也日趋突出,成为实现视频系统小型化、轻量化、高性能和高可靠的有效方法.针对当前RF SiP（射频系...     

A Novel GCPW to Rectangular Waveguide Transition for 60 GHz Applications

A new type of grounded coplanar waveguide (GCPW) to rectangular waveguide transition in an LTCC multi-layer structure for 60 GHz applications is proposed in this letter. The GCPW and rectangular waveguide are fully integrated on the same substrate, and the ground wall of the rectangular waveguide is made up of a staggered via fence. The transition is accomplished by inserting a bent short stub. We analyze and prove the novel transition structure by applying an equivalent circuit model. Measured results for a single transition show that the insertion loss is 0.345 dB at 59 GHz and the bandwidth is 6.3 GHz. The proposed transition structure with very low loss at a large bandwidth is very suitable for a SiP of 60 GHz WPAN applications.      

LTCC在SiP中的应用与发展

SiP是实现先进电子设备小型化、多功能化和高可靠性的有效途径。SiP的组装和封装载体是基板。LTCC通过采用更小的通孔直径、更细的线宽/线间距和更多的布线层数能实现SiP复杂系统大容量的布线。通过采用空腔结构可以优化系统元器件的组装,提高散热能力。利用埋置无源元件,可以减少SiP表贴元件的数量。利用3D-MCM和一体化封装可以进一步减少系统的面积和体积,缩短互连线。未来SiP的发展要求LTCC具有更好的散热能力、更高的基板制作精度和更多无源元件的集成。     

产品导向的先进封装设计

在日益激烈竞争的电子工业中,高成本效益、高可靠性的电子封装方案不单是电子产品发展的主要驱动力,甚至往往成为当中的促成科技(EnablingTechnology),用于轻巧、细小的无线电/可携带式消费性电子产品中尤见适合。其中更理想的性能效益(cost/performanceratio)、更短的产品开发周期、集多功能于一身的消费性电子产品亦是崭新科技应用的主要原动力。要达到以上目标,相关的微电子封装方案与焊接技术的进步是不可或缺的:例如从金属线焊接技术发展到倒装芯片技术,及至近年的晶圆级封装技术;从外围焊接(peripheral)发展到数组焊接(area-array);从陶制基版发展到有机基版;从单芯片封装发展到复芯片封装的构装方案等。事实上,系统级封装比一般的封装方案拥有一定的优势。在报告中首先概述最近在系统级封装的发展情况与应用。另外,借此报告突显出跟供应链有关产业之间的密切协调是达到有效而迅速地执行系统级封装的关键。最后,在报告中进一步详述一个集顶尖封装设计、分析及可靠性评估技术的服务中心的好处,及如何对工业界从事原型设计发展到大量生产的协助。     

Evaluation of the Delamination in a Flip Chip Using Anisotropic Conductive Adhesive Films Under Moisture/Reflow Sensitivity Test

Anisotropic conductive adhesive films (ACFs) have been used for electronic assemblies such as the connection between a liquid crystal display panel and a flexible printed circuit board. ACF interconnection is expected to be a key technology for flip chip packaging, system-in-packaging, and chip size packaging. This paper presents a methodology for quantitative evaluation of the delamination in a flip chip interconnected by an ACF under moisture/reflow sensitivity tests. Moisture concentration after moisture absorption was obtained by the finite element method. Then, the vapor pressure in the flip chip during solder reflow process was estimated. Finally the delamination was predicted by comparing the stress intensity factor of an interface crack due to vapor pressure with the delamination toughness. It is found that the delamination is well predicted by the present methodology.     

A high resolution method for measuring hot carrier degradation in matched transistor pairs

A new measurement methodology has been developed in order to perform high-resolution measurements of the hot carrier degradation on MOSFET's. With this methodology, degradations as low as 0.01% can be measured accurately. The high resolution measurements are necessary for measuring hot carrier degradation in matched transistor pairs. This is demonstrated by comparing the degradation at different stress conditions. A linear extrapolation is not applicable when extrapolating the degradation curves from 1 % to 100 ppm.