要明星还是要故事？

所以,大家最好用平常心来看明星制。于票房而言它很重要,但不绝对。偏重明星或偏重故事,无疑也反映着观众的欣赏倾向和审美趣味。某年,天津一位腕级作家去参加中国作协组织的培训班,和某外地作家同居一室。大家白天听讲座,晚上写自己的长篇,彼此间不免交流交流。有一天这位天津作家忽然发现,同室作家把自己小说里的女主人公从妙龄少女改成中年妇女,便问他这么改是出于何种构思?同室作家笑笑说,没什么特别的构思。有人要把这部小说改成电视剧,并且定好请倪萍主演,我得围绕她重新编故事!     

中国移动玩转固网业务 要规模还是要利润?

作为固网领域的后起者,中国移动相比竞争对手在基础资源储备方面较弱,面对盈利模式相对单一且投资巨大的固网市场,中国移动应先扩规模还是先要利润？     

2022年手机市场要创新还是要规模?

在日前举行的2022年世界移动通信大会上,OPPO发布了创纪录的150W和240W闪充技术,从而拉开了今年手机产业和国内手机厂商创新的序幕.那么今年手机产业创新和市场的走向如何? 提到2022年的手机创新,相信折叠屏技术肯定是首屈一指,且颇具代表性. 众所周知,2021年荣耀、OPPO、小米等品牌都发布了折叠屏手机,对...     

现实与理想的差距,玩游戏要分辨率还是要反锯齿?

充满神奇色彩的3dfx,如同他们静悄悄地开始进入3D芯片领域带给人们的惊奇一样,AA(反锯齿)成为他们走之前留给我们的最后财富。AA技术是一种相对特别的技术,与类似T&L这样的新技术(用于游戏)不同的是,AA基于更高分辨率的虚拟渲染,而不需要新的指令和重写新的函数,只与显卡本身有关。来源于这种良好的概念,这个技术具有良好的兼容性以及与具体的游戏无关的支持特性,能让任何游戏在3D品质上获益,特别是在低分辨率下,AA更成了能够提高3D品质的神器,让很多游戏玩家即使是在玩过去的游戏也会对画面大呼过瘾。AA的神妙之处就在于此,这多少让…     

相片还是要冲出来

赞叹电脑强大存储功能的同时,也害怕它生气抛锚,让先前的存储变得毫无意义。而冲印的照片伴着春夏秋冬来去,覆着大自然的气息,发散着浓郁的味道,是怀念,是温馨,是幸福,是见证,是真实的存在,这是一个人一生情感的记忆,因为这微黄的相片得以延续。     

男人!还是要动手

整洁俊朗、翩然优雅的男子固然令女人心醉，同类心碎!不过有时换衣挽袖，污泥油腻操持着酷酷什物，那专注的神情，迅捷的身手，非常态的姿势也变得性感迷人，所以男人，动起手，增加你的厚重感吧!     

要品牌机还是兼容机？

品牌机还是兼容机? 这个讨论由来已久了,而且观点上好像十分明确——打倒品牌机! 其实仔细想一想,为什么这样的观点会充满我们的耳边?其实很简单,因为写这种文章的人都是对电脑比较精通的,他们对硬件结构比较熟悉,因此能够比较自由的进行电脑的搭配,总认为自己DIY可以有更广阔的空间,可以得到更低廉的价格。然而,他们的看法对每个人都有效吗?当然不是。应该说笔者也是DIY阵营中的一员,不过在笔者看来,DIY"便宜"已     

企业:要狼性还是要人性

和世界任何其他地方的企业家相比,中国的企业家更愿意将企业的经营和战争、政治相提并论,在后者眼里,企业经营就是一场战争,就是政治斗争。没有人去研究这个现象背后的内在本质。我想,中国企业家的这个心态一方面与中国人好斗的性格有关,一方面可能和他们生存的环境有关。中国人创造了象棋和围棋,但是厮杀更为激烈的象棋在中国最为普及;扑克牌传到     

企业：要狼性还是要人性

和世界任何其他地方的企业家相比,中国的企业家更愿意将企业的经营和战争、政治相提并论,在后者眼里,企业经营就是一场战争,就是政治斗争。没有人去研究这个现象背后的内在本质。我想,中国企业家的这个心态一方面与中国人好斗的性格有关,一方面可能和他们生存的环境有关。     

M.O.S. bucket-brigade AND?OR logic array

An integrated m.o.s. bucket-brigade logic array capable of performing both AND and OR functions is described. The operation of the array is discussed and experimental results are presented.     

A mobile-radio space-diversity receiving system using delta modulation with a "STAR" type cophasing scheme

A multiple branch predetection combining diversity receiver technique using pulse-envelope modulation of the transmitted signal is described. The receiver branches use the "STAR" scheme of multiple heterodyning of the received signal with itself to eliminate all exponential modulation components imparted by the transmission medium. Each branch can be shown to be mathematically equivalent to a simple square-law detector. A modulation scheme using low-bit-rate (50 kHz) companded delta modulation is proposed which provides a reasonable output signal-to-noise ratio (30-40 dB). The convenience of received signal gain control before pulse regeneration and the possible application of conjugate phase retransmission could make this technique useful.     

A decoder with OR gates for a Josephson high-density memory circuit

A decoder made of OR gates was designed for a Josephson high-density memory circuit. The advantages of this decoder are its large operating margin and high-speed operation compared with conventional decoders made of AND gates. The decoder was designed for a 16-Kbit random access memory (RAM), and was successfully operated with a delay time of 2 ns.     

A block code for noiseless asynchronous multiple-access OR channel (Corresp.)

A Mock code for the noiseless multiple access OR channel is introduced. An exponential error bound is proven if the sum of the equal code rates of the asynchronousTusers is less thanln 2.     

Design of all-optical AND,OR, and XOR logic gates using photonic crystals for switching applications

Photonic Network Communications - We propose a photonic crystal-based all-optical AND, OR, and XOR logic gates using square lattice silicon rods with air background. The design of proposed logic...     

A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates

In this paper, a new charging scheme for reducing the power consumption of dynamic circuits is presented. The proposed technique is suitable for large fan-in gates where the dynamic node discharges frequently. Simulation results demonstrate that the proposed method is efficiently controlling the internal voltage swing and hence decreasing the power consumption of the wide fan-in OR gate without sacrificing other circuit parameters such as gate speed, area or noise immunity. The power-delay product of a simulated 8-input OR gate is reduced by 46%, compared to its conventional dynamic counterpart in the 90 nm CMOS technology. Another important benefit of the proposed approach is 99X reduction in power dissipation of the gate load by limiting its switching activity. Furthermore, the delay of the proposed circuit experiences only 0.94% variation over 10% fluctuation in the threshold voltages of all transistors for a 32-bit OR gate. Using the proposed technique, a 40-bit tag comparator is simulated at 1 GHz clock frequency. The power consumption of the designed circuit is as low as 1.987 µW/MHz, while the delay and unity noise gain (UNG) of the circuit are 244 ps and 499 mV, respectively.