AD7677在变送器校验装置直流测量系统的应用

高精度的A/D转换器是实现高精度测量的前提,AD7677是16住高速,高精度A/D转换器.介绍了MD7677的主要特性及其在变送器校验装置直流测量系统中的应用设计.     

15十位转换器的噪声整形编码器拓朴

本文介绍了可用标准数字集成电路工艺集成的高精度噪声整形转换器的一种新颖的拓朴。这种拓朴采用一个多位噪声整形编码器和一种新式的动态元件匹配,以实现高精度和长期稳定性,而毋需采用精密的匹配元件。采用一个3位量化器和一个动态元件,匹配内部D/A转换器的4级噪声整形D/A变换系统,用标准的两次金属3μCMOS工艺制造,可达到16位动态范围,其谐波失真低于-90db。这种多位噪声整形D/A变换系统所达到的性能可与工作于约为其时钟频率四倍的1位噪声整形D/A变换系统的性能媲美。     

基于平均功率谱的高精度A/D转换器动态参数测试

讨论了窗函数处理在基于FFT变换的高精度A/D转换器动态参数测试中的不足,提出了基于平均功率谱的高精度A/D转换器动态参数测试方法,并从理论上证明了该方法可以有效降低FFT变换测试方法中由于采用窗函数处理引入的噪声误差。最后,以ADI公司的16位A/D转换器AD9260为例,对其信噪比和总谐波失真等动态参数进行了测试实验验证。     

一种抗辐射16位80 MSPS A/D转换器设计

为满足航天电子系统对高速高精度16位A/D转换器的需求,设计了一种流水线型16位80 MSPS A/D转换器,内核采用“3+4+3+3+3+3+3”七级流水线,前端缓冲器用于减小第一级MDAC采样网络回踢信号对A/D转换器线性度的影响。采用环栅器件、N+/P+双环版图等设计加固技术。A/D转换器采用0.18 μm CMOS工艺,工作电源电压为3.3 V和1.8 V,在时钟输入频率为80 MHz和模拟输入频率为36.1 MHz时,ADC的功耗≤1.1 W、信噪比SNR≥73.8 dB、无杂散动态范围SFDR≥88 dBFS。电离总剂量150 krad(Si)辐照后,ADC的信噪比SNR变化量≤0.3 dB、无杂散动态范围SFDR变化量≤1 dB;Bi离子辐照下ADC的电流增加≤4 mA。     

基于PIC单片机与AD7884的ADC系统

本文主要介绍了一种采用余弦反馈比较式原理的高速、高精度的16位A/D转换器AD7884的性能和工作原理.并把其与单片机PIC16C66相结合,构成了高精度、多通道ADC系统,实现了数据采样及其转换传输.     

CS5522型A/D转换器及其在小角度测量中的应用

CS5522是24位高精度△-∑型串行A/D转换器.文中介绍了CS5522型A/D转换器的主要性能、引脚构成、内部寄存器及校准方法.结合CS5522型A/D转换器在小角度测量中的实际应用,给出了CS5522型A/D转换器与单片机的接口及系统电路图,最后给出了试验数据.     

12位A/D转换器ADS774JP及其在高精度检测系统中的应用

ADS774JP是美国Burr -Bown公司生产的12位A/D转换器 ,它所需外围器件少、接口方便且运算速度快 ,可用于高精度检测系统。文中介绍了12位A/D转换芯片ADS774JP的主要特点 ,分析了ADS774JP的转换时序 ,给出了该转换器在高精度微机检测系统中的硬件接口电路和软件程序     

一种用于高精度D/A转换器的数字校准技术

介绍了一种用于400MSPS16位高精度电流舵D/A转换器的数字静态校准技术。该校准技术利用地址产生器、钟控比较器、SAR寄存器和校准DAC,构成逐次逼近式校准环路。利用该校准环路,可以自动完成高7位电流源阵列单元的校准,从而极大地提高电流源的匹配性。采用该校准技术的16位电流舵D/A转换器的DNL大于±0.5LSB,达到了真正的16位精度。     

面向音频应用的可配置片上系统的设计与实现

基于一款通用的16位定点数字信号处理器,结合D/A转换器、A/D转换器和放大器等模拟电路模块,设计并实现了一种面向音频应用的可配置片上系统.该系统支持立体声输入输出,具有8～48 kHz之间可编程的采样频率,以及可编程的输入输出放大器增益.同时,设计使用了24位高精度Σ-Δ A/D转换器,并配有可供选择的数字滤波器.为支持不同应用,系统提供24位或16位的可编程字长调节.系统芯片工作在1.8 V电压下,芯片内各部分支持挂起或睡眠状态,有利于低功耗的便携式应用开发.介绍了部分关键功能模块的仿真、验证和测试,以及整个系统仿真模型的建立.     

一种基于CMOS工艺的抗辐照A/D转换器

空间辐射对电子系统的损伤是航天设备发生故障的重要因素。A/D转换器是航天电子系统的关键器件之一,其抗辐射性能将直接影响航天设备的整体性能。基于标准0.35 μm CMOS工艺,设计了一种流水线型14位A/D转换器,从总体架构、关键核心单元、版图等方面进行抗辐照设计。辐照测试结果表明,该A/D转换器的抗总剂量能力达到1.0 kGy(Si),抗单粒子闭锁阈值达到37 MeV·cm²/mg,满足宇航电子系统的应用要求。     

A/D转换器非线性特性简易测试方法

A／D转换器非线性测试是A／D转换器静态特性测试的一项重要内容。相对于以往成本较高的测试方法，文章提出了一种简易可行的测试方法：利用高精度D／A转换器和低精度A／D转换器的精度差，借助8051仿真系统进行测试。实验表明，该方法成本低廉，操作简单，适用于A／D转换器非线性特性的初期评测。     

A noise-shaping coder topology for 15+ bit converters

A topology for high-precision noise-shaping converters that can be integrated on a standard digital IC process is presented. This topology uses a multibit noise-shaping coder and a novel form of dynamic element matching to achieve high accuracy and long-term stability without requiring precision matching of components. A fourth-order noise-shaping D/A (digital-to-analog) conversion system using a 3-b quantizer and a dynamic element-matching internal D/A converter, fabricated in a standard double-metal 3-μm CMOS process, achieved 16-bit dynamic range and a harmonic distortion below -90 dB. This multibit noise-shaping D/A conversion system achieved performance comparable to that of a 1-bit noise-shaping D/A conversion system that operated at nearly four times its clock rate     

Design and test methodology for an analog-to-digital convertermultichip module for experimental all-digital radar receiver operatingat 2 gigasamples/s

In this paper, we describe the development of an analog-to-digital (A/D) converter subsystem, based on a monolithic A/D converter chip, a demultiplexer chip, and a laminate multichip module, for an experimental all-digital receiver for an airborne radar. The evolution of techniques for recording and analyzing all the data from the assembled multichip module at the full sample rate of the A/D converter, and the ways in which this test data can be used to analyze the performance of A/D converters, are described. The problems which arise in the testing of GHz A/D converters, a number of which are unique to A/D conversion at such high sample rates, are pointed out. Finally, comments on future directions in the test of high performance A/D converters are presented     

基于ATE的8位超高速ADC动态参数测试

提出了一种采用Advantest 93000型自动测试设备,配合外挂高性能信号源SMA 100A,对8位1.5 GS/s超高速ADC进行动态参数测试的方案。该方案使用外挂信号源,提供采样时钟和模拟输入信号,解决了93000与外部信号源之间输入信号不同步,以及两者频率差异导致的采样不稳定问题,有效提升了93000测试超高速ADC动态参数的能力,可广泛应用于超高速ADC量产测试。     

A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters

Testing high-speed A/D converters for dynamic specifications needs test equipment running at high frequency. In this paper, a methodology to test high-speed A/D converters using low-frequency resources is described. It is based on the alternate testing approach. In the proposed methodology, models are built to map the signatures of an initial set of devices, obtained on the proposed low-cost test set-up, to the dynamic specifications of the same devices, obtained using high-precision test equipment. During production testing, the devices are tested on the low-cost test set-up. The dynamic specifications of the devices are estimated by capturing their signatures on the low cost test set-up and processing them with the pre-developed models. As opposed to the conventional method of dynamic specification testing of data converters, the proposed approach does not require the tester resources running at a frequency higher than the device-under-test (DUT). The test methodology was verified in simulations as well as in hardware with specification estimation error of less than 5%.

A/D转换技术的应用与发展

首先分别介绍了当前六大模数转换技术的工作原理、电路结构、性能特点及应用领域,通过从转换速率、转换精度、分辨率、功耗、价格、面积等指标进行分析,将物理结构的设计与实际性能结合比较,总结出各自适合的应用领域.然后,根据对现有模数转换技术特点的分析及实际应用中对模数转换器性能的要求,对当前A/D转换技术向着高性能、低功耗、结构简单方向发展的趋势进行了预测.     

基于ATmega16L的电液伺服控制系统设计

针对电液伺服闭环控制过程中,设定信号不断发生变化,电液阀门位置定位精确度较低的难题.采用AT-mega16L作为核心控制器,并配有高精度A/D、D/A转换器,通过对阀门开度控制信号和位置反馈信号进行采集、转换、计算和比较,发出控制信号决定并执行换向阀的换向、交流伺服电动机的起停运转,推动液压缸推杆的伸缩,进而对阀门转角大小、开度百分比进行精确定位.     

Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

Static testing of analog‐to‐digital (A/D) and digital‐to‐analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built‐in self‐test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.     

Zero-Crossing-Based Ultra-Low-Power A/D Converters

Since the first demonstration of a comparator-based switched-capacitor circuit, analog-to-digital (A/D) converters based on virtual ground detection have made steady and significant progress. Comparators have been replaced by zero-crossing detectors, leading to the development of zero-crossing based circuits for faster speed and lower power. All facets of performance including the sampling rate, effective number of bits, noise floor, and figure-of-merit have improved substantially. This paper focuses on recent implementations of zero-crossing based A/D converters and discusses the technical issues unique to these A/D converters as well as solutions that have been developed to improve their performance and practicality. A series of prototype designs whose performance ranges from 8 bit, 200 MS/s to 12 bit, 50 MS/s are described. The ultimate low power potentials of these A/D converters are compared with various different types of complementary metal–oxide–semiconductor A/D converters from a fundamental thermal noise standpoint.      

Effects of Quantization in Systolic 2D IIR Beam Filters on UWB Wireless Communications

Ultra-wideband (UWB) wireless beamforming systems may potentially be implemented digitally at multi-gigahertz clock frequencies using low-precision systolic array realizations of two-dimensional (2D) infinite impulse response (IIR) beam plane-wave filters. The finite precision performance of such filters is analyzed in terms of quantization noise. Extensive Monte Carlo simulations are performed using test vectors that are derived from 2D finite-difference time-domain (FDTD) computational electromagnetic models of the UWB channels. The bit error rate (BER) is determined as a function of signal-to-interference ratio (SIR), with and without beamforming, and for various practical combinations of finite internal wordlengths and A/D converter precisions. It is established that 3-bit A/D converters with 3- to 6-bit internal wordlengths are adequate for good performance and that 4-bit A/D converters with 4- to 7-bit internal wordlengths achieve excellent performance.