埋入电容印制板工艺技术

本篇文章讨论的是采用两种基材制作四层埋入电容印制板的方法FR-4基材和FR-406电容材料分别经过单面 图形转移,再经层压到外层制作的路线完成此四层板尺寸变化较小,能够很好地配合高层数多层板的工艺制作。     

一种新型的单面蚀刻技术制备埋容电路板

介绍了一种新型的埋入电容电路板的单面蚀刻工艺。本工艺主要针对介质层厚度≤50μm的埋入电容材料,在制作单面图形时,不去掉未曝光一面的干膜及干膜保护膜,棕化后再过显影线将干膜去掉。对该工艺可行性进行了评估,并验证了其可靠性。实验结果表明,采用此工艺可以减少工艺难度,加工成本降低了3%,且产品合格率达86%以上。     

平面埋入电容的印制电路板研究

文章介绍以有机/无机复合薄膜作为电介质层的埋入式平面电容,其结构为金属-介质-金属,其具有与印制电路板制造工艺的良好兼容性,采用层压法进行平面埋入式电容的制作,其工艺简单,制作成本较低,可实现大规模量产。     

埋入电容式多层印制板的研制

研究埋入电容多层板的制作工艺。通过试验验证电容容值与电容设计方法的关系,多层板生产流程中层压、热风整平工序对电容容值的影响;通过热冲击试验、老化试验等试验验证了埋入电容的容值在环境试验中的稳定性。通过一系列试验验证了埋入电容具有高温稳定性,可以在多层板内实现多个埋置电容层。可靠性试验证明埋置电容具有很好的稳定性和很高的可靠性。     

铁电微电容的制作工艺

研究了铁电电容的制作工艺，摸索了Ｐ（Ｌ）ＺＴ铁电薄膜及上、下电极材料的微细图形加工工艺条件，总结出切实可行的工艺流程及相应的工艺条件。     

高频埋容PCB制作关键技术研究

高频埋容PCB制作是线路板制造行业中十分重要的技术,国内多家线路板厂家也有生产,但是涉及到层数较高的高频埋容PCB的制作还是鲜有听闻.究其原因主要有两点:(1)目前在PcB中还无法埋入较大电容值的电容,需要开发功能值大的埋入元件材料:(2)埋入平面电容的容值误差控制较难,尤其是丝网漏印的平面型埋容元件材料的功能误差控制十分困难.丈章以一款24层高频埋容板为例,探究高频埋容PCB制作关键技术.     

双面蚀刻薄介质材料埋容芯板可行性研究

用蚀刻薄膜材料法制作埋嵌式电容，其电容介质材料较薄，常用的电容介质材料厚度在8μm～50μm之间，因此在制作电容层图形时，容易出现皱折、破损的情况。目前可行的方法是用单面蚀刻法制作电容层图形。探讨运用双面蚀刻法制作电容层图形对电容值精度的影响及其可行性分析。     

高密度低寄生电感硅基半导体电容器的设计及验证

采用在半导体材料表面深刻蚀三维图形以形成稳固蜂窝结构的方法,研究了一种适用于解决高频电路和系统级封装中串扰耦合问题的高密度、低寄生电感、制作及排布容易的硅基电容。结果显示,所制作的电容,其密度可增大至普通平面半导体电容的10倍以上,并较大程度地降低了电容的寄生电感,使其性能大大优于常用商业陶瓷电容,更适用于高频电路和系统级封装中的有效退耦。     

一种可集成高密度氮氧化硅介质工艺

针对传统二氧化硅、氮化硅等介质材料在制作MOS电容时存在电容密度低、界面特性差的问题,通过对氮离子注入、氮硅氧化实验的分析,成功开发出一种采用注入氮并氧化制作氮氧化硅介质材料的工艺;并使用该工艺研制出与36 V双极工艺兼容、介质的相对介电常数为5.51、击穿电压达81 V、电容密度为0.394 fF/μm²的高密度MOS电容,较传统可集成二氧化硅/氮化硅复合介质电容的电容密度提高了35.86%。该工艺还可用于制作大功率MOSFET的栅介质,可提高器件的可靠性。     

浅谈埋电容PCB的制作工艺

埋电容技术作为PCB制作的一种新工艺。PCB内埋电容不仅节省了PCB板面空间,同时还大量减少了PCB板面SMT焊点数目,提高了PCB板件的可靠性。因目前市场上推出的埋电容材料,由于芯板较薄,通常介质层厚度≤50μm,薄芯板的特性使材料在PCB加工过程中存在一定的难度。本文选用一种陶瓷粉填充的埋电容材料,对该种材料制作埋电容的PCB加工工艺进行相关的研究。     

Ultrathin oxide-nitride dielectrics for rugged stacked DRAMcapacitors

Ultrathin dielectric materials that provide high capacitance values are needed for 64- and 256-Mb stacked DRAMs. It is shown that capacitance values as high as 12.3 fF/μm² can be obtained with ultrathin nitride-based layers deposited on rugged polysilicon storage electrodes. These films present the reliability and low leakage current levels required for 3.3-V applications. The nitride thickness, however, cannot be scaled much below 6 nm to avoid the oxidation-punchthrough mechanisms that appear when too-thin films are unable to withstand the reoxidation step     

Nitrogen‐Doped Carbon Networks for High Energy Density Supercapacitors Derived from Polyaniline Coated Bacterial Cellulose

Bacterial cellulose (BC) is used as both template and precursor for the synthesis of nitrogen‐doped carbon networks through the carbonization of polyaniline (PANI) coated BC. The as‐obtained carbon networks can act not only as support for obtaining high capacitance electrode materials such as activated carbon (AC) and carbon/MnO₂ hybrid material, but also as conductive networks to integrate active electrode materials. As a result, the as‐assembled AC//carbon‐MnO₂ asymmetric supercapacitor exhibits a considerably high energy density of 63 Wh kg^?1 in 1.0 m Na₂SO₄ aqueous solution, higher than most reported AC//MnO₂ asymmetric supercapacitors. More importantly, this asymmetric supercapacitor also exhibits an excellent cycling performance with 92% specific capacitance retention after 5000 cycles. Those results offer a low‐cost, eco‐friendly design of electrode materials for high‐performance supercapacitors.     

10 gbit/s 0.0065 mm2 6 mw analogue adaptive equaliser utilising negative capacitance

An area- and power-efficient analogue adaptive equaliser (AEQ) is realised in a 0.13 μm CMOS technology. The negative capacitance circuits are exploited at the equalisation filter to achieve wider bandwidth and larger high-frequency boosting, instead of using passive inductors that lead to a large chip area. Measured results demonstrate the data rate of 10 Gbit/s for 20 and 34 inch FR4 traces as channels, while dissipating only 6 mW from a single 1.2 V supply. The chip core occupies an extremely small area of 50 x 130 μm². To the best of the authors' knowledge, this chip achieves the lowest power consumption and the smallest chip area among the recently reported AEQs.     

A comparison of quantum-mechanical capacitance-voltage simulators

We have systematically compared the results of an extensive ensemble of the most advanced available quantum-mechanical capacitance-voltage (C-V) simulation and analysis packages for a range of metal-oxide-semiconductor device parameters. While all have similar trends accounting for polysilicon depletion and quantum-mechanical confinement, quantitatively, there is a difference of up to 20% in the calculated accumulation capacitance for devices with ultrathin gate dielectrics. This discrepancy leads to large inaccuracies in the values of dielectric thickness extracted from capacitance measurements and illustrates the importance of consistency during C-V analysis and the need to fully report how such analysis is done     

Comb Capacitor Structures for On-Chip Physical Uncloneable Function

Planar inter-digitated comb capacitor structures are an excellent tool for on-chip capacitance measurement and evaluation of properties of coating layers with varying composition. These comb structures are easily fabricated in a single step in the last metallization layer of a standard IC process. Capacitive coupling of these structures with a coating layer is modelled based on the electric field distribution to have a detailed understanding of contributing capacitance components. The coating composition is optimized to provide maximum spread in capacitance values of comb capacitor structures. This spread in measured capacitance values can be used to implement a physical uncloneable function (PUF). A PUF is a random function which can be evaluated only with the help of a physical system. We present an on-chip capacitive PUF for chip security and data storage in which the unlock key algorithm is generated from capacitors which are physically linked to the chip in an inseparable way. The strength of this key increases with the spread in capacitance values and measurement accuracy.      

超级电容器用竹炭的制备及其电容性能

以竹材为原料,在高温Ar保护下制备了高比表面积超级电容器用竹炭材料。用XRD和SEM对所制竹炭进行了物相分析和形貌观察;用循环伏安、恒电流充放电和交流阻抗谱研究了炭化温度对所制超级电容器性能的影响。结果表明:所得竹炭为无定形结构,随着炭化温度的升高,竹炭中石墨微晶向有序态结构发展。炭化温度为500℃时,制备的竹炭电性能最佳。在125mA/g电流密度下的首次放电比电容为226F/g;即使在500mA/g的大电流密度下,其放电比电容仍高达184F/g,第1000次循环时其放电比电容为138F/g,每次循环电容衰减仅为0.046F/g。     

A new pulse sequence for "fast recovery" fast-scan NMR imaging

This paper describes the "fast recovery" (FR) method for fast NMR imaging. The FR method combines a sequence of four RF pulses-alternating selective 90 degrees nutation pulses and nonselective 180 degrees pulses-with a gradient field pulse sequence which includes "spoiler" pulses to destroy the coherence between successive sequence cycles. We use the 2-D backprojection method of image reconstruction, but other imaging methods could be applied. The paper analyzes the behavior of the macroscopic magnetization-compares the FR method with other methods and proposes "figure of merit" expressions for relative signal-to-noise (S/N) ratios, scan time reduction ratios, and image contrast-and presents experimental results, including backprojection image reconstruction 2-D images and computed T1 and T2 images. For the FR method, in theory and practice, we find that, after each scan sequence cycle, magnetization is restored to equilibrium quickly and exactly; scan time can consequently be less than a tenth that for the saturation recovery method without any penalty in signal-to-noise ratio. Image contrast is even higher than that of the SR method, and compromise "optimum" sequence (interpulse timing) parameters give high image contrast for a wide range of tissue T1 and T2 (spin-lattice and spin-spin relaxation time) values.     

A floating well method for exact capacitance-voltage measurement of nano technology

Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.     

A new equivalent MOSFET representation of a HEMT to analyticallymodel nonlinear charge control for simulation of HEMT devices andcircuits

It is shown that, from the point of view of the behavior of the charge and position of the Two-Dimensional Electron Gas (2-DEG) as a function of gate-source and drain-source voltages, the complex High Electron Mobility Transistor (HEMT) can be regarded as a simple Buried-Channel (BC) MOSFET. Thus, the characteristics of a HEMT, namely channel charge and capacitance/transconductance as a function of gate voltage below and above threshold are akin those of a BC MOSFET. Hence, there are discrepancies in the conventional Surface Channel MOSFET-like approach to HEMT modeling. Existing simple BC MOSFET dc and ac models can be used for on-paper analysis and computer aided simulation of HEMT devices and circuits, if the HEMT is represented by an equivalent BC MOSFET as derived in this paper. The new representation can be useful for modeling of short-channel HEMT phenomena