Novel interface nitridation process for thin gate oxides

A thin (100-200-Å) gate dielectric film which exhibits improved properties as compared to control pure thermal oxides is discussed. The film is obtained by thermal nitridation of the silicon wafers in pure ammonia, followed by high temperature oxide (HTO) deposition, and an anneal in oxygen ambient (reoxidation). It was found that these dielectrics exhibit excellent electrical characteristics under Fowler-Nordheim tunneling stress, such as a relatively large charge-to-breakdown considerable reduction in charge trapping, reduction of interface state generation, and a significantly improved resistance to transconductance degradation. The dielectric layer is of potential use for the fabrication of reliable ultrathin gate oxide films for standard CMOS technology and particularly for nonvolatile programmable memories     

Effect of N2O nitridation on the electrical properties of MOS gate oxides

Furnace annealing in N₂O is a convenient technique for improving the reliability of thermal oxides without significant modifications of the process flow. We investigate the impact of N₂O nitridation on MOSFET device performance, assessing the various factors contributing to the observed degradation of electron mobility. Estimates based on low-frequency C-V and charge pumping measurements show that nitridation causes a significant increase of the interface trap density in the vicinity of the conduction band. Interface traps contribute a parasitic component to the gate-channel capacitance, thus leading to an overestimate of the inversion charge. This effect accounts for a substantial fraction of the mobility degradation which is observed for the nitrided devices. The remaining degradation can be ascribed to an enhancement of Coulomb scattering, maybe due to differences in dopant segregation, and to a change of the surface roughness characteristics.     

Effect of postoxidation annealing on the reliability of rapidthermal thin gate oxides

The reliability of thin gate oxides grown by rapid thermal oxidation in O₂ followed by one and two step postoxidation annealing (POA) in N₂ was studied. The one step POA was carried out by switching O₂ into N₂ immediately after oxidation without changing temperature, while the two step POA was cooled down first and subsequently heated to the same temperature as oxidation in N₂. It was experimentally observed that the oxide thickness increases significantly with the POA time in one step POA, while the oxide thickness shows very little change during two step POA. The interfacial properties and the oxide breakdown endurance can be improved by the two step POA. Also, the radiation hardness of oxide is less degraded by the two step POA than by one step POA. The effect of oxide thickness variation due to POA is chiefly responsible for the observation and is important to thin gate oxides     

Influence of fluorine contamination on reliability of thin gate oxides

We analyze diffusion and segregation kinetics of fluorine atoms in poly-Si / SiO₂ / Si structures with gate oxides of 5 nm by means of secondary ion mass spectroscopy. Well defined doses of fluorine were introduced by ion implantation. Our results indicate fluorine segregation at interfaces to the gate oxide. This segregation is diffusion limited with an effective activation energy of 1.4 eV. The accumulation of fluorine influences the intrinsic reliability of thin oxides. The breakdown behavior was studied using constant voltage, constant current, and stepwise increasing constant current stress, respectively. Weibull plots before and after the heat treatments were analyzed. At low fluorine concentrations up to doses of 5 × 10¹⁵ cm⁻² fluorine segregation is beneficial, improving, for example the tails of the Weibull plots and slightly increasing the breakdown voltage. For fluorine doses higher than 1 × 10¹⁶ cm⁻², detrimental consequences were found, degrading the charge to breakdown values by about a factor of 5 after long - term thermal treatments.     

Ultra-thick gate oxides: charge generation and its impact on reliability

In this work, degradation and breakdown characteristics of ultra-thick gate oxides (T_ox: 50–150 nm) used in power MOS devices is investigated. Measurements indicate, that in addition to charge generation via Fowler–Nordheim tunneling, a second mechanism becomes dominant in ultra-thick gate oxides even at moderate electrical fields (i.e. 7–8 MV/cm). The results suggest, that impact ionization and related electron–hole pair creation by energetic electrons is responsible for the experimental observations. The impact of these results on the interpretation of lifetime extrapolations from accelerated tests will be discussed.     

Post poly-Si gate rapid thermal nitridation for boron penetrationreduction and oxide reliability improvement

Boron penetration from p⁺ doped poly-Si gates in PMOSFET is greatly reduced by post poly-Si gate rapid thermal nitridation. Gate oxide reliability against boron penetration is significantly enhanced. When post poly-Si nitridation is combined with N ₂O annealed gate oxides, gate oxide charge-to-breakdown is markedly improved     

Electrical reliability aspects of through the gate implanted MOS structures with thin oxides

The effect of through the gate implantation (TGI) on MOS devices with oxide thicknesses of 3.3, 4.0, and 20 nm is studied, utilizing constant voltage stress tests and a substrate hot electron (SHE) injection technique. For 3.3 and 4.0 nm thick oxides, a dependence of time to breakdown on TGI dose is detected which, for 3.3 nm samples, diminishes with increasing test voltage. SHE injection measurements show a TGI induced increase in intrinsic electron trap density and also an increase in trap generation rate during sample stressing. A change of electron trap generation dynamics seems to be the main cause for oxide weakening due to TGI.     

Wet or dry ultrathin oxides: impact on gate oxide and device reliability

In this study, wet and dry oxidation processes for 3.5 nm ultrathin dielectrics are compared in terms of oxide and device reliability. It is demonstrated that a wet oxidation enables to strongly improve the oxide lifetime. On the contrary, the device reliability has been found to be slightly affected by the process choice. Finally, these results associated with charge pumping and stress induced leakage current measurements indicate that the bulk oxide, more than the Si/SiO₂ interface, is affected by the growth process ambience (wet or dry oxidation).     

Voltage-splitting technique for reliability evaluation of off-state mode of MOSFETs in ultrathin gate oxides

A simple and practical new methodology is proposed for reliability evaluation of off-state mode in ultrathin oxides. By applying a negative voltage on the gate while the drain region is biased at the operating voltage; the so-called voltage-splitting technique (VST), we successfully resolve the difficulty associated with the unrealistic high drain-bias stress otherwise required, which leads to the excessive damage to oxide integrity in the overlap region. In comparison with a high drain-bias stress, the time-dependent dielectric breakdown measurements using VST show the well-behaved breakdown distribution and correlate with the measured device characteristics. In addition, this methodology may provide a possible method to extrapolate stress data to operational voltage for realistic off-state reliability projection.     

A study of interface trap generation by Fowler-Nordheim andsubstrate-hot-carrier stresses for 4-nm thick gate oxides

The generation of interface traps by different stresses to 4-nm thick SiO₂ gate oxide is studied. Four different kinds of constant current stresses were applied. The interface-trap density (D _it) generation due to hot holes under V_G<0 Fowler-Nordheim (FN) stress was characterized using quantum-yield measurement and substrate-hot-hole (SHH) stress. The interface-trap density (D_it) generated by SHH stress increases as gate-oxide field increases. Substrate-hot-electron (SHE) stress generates much less interface-trap density (D_it) than SHH stress. It is also observed that N₂O-grown gate-oxide has smaller hole-injection probability but larger electron-injection probability than O₂-grown oxide. N₂O-grown gate oxide is shown to have less SHH stress-induced interface traps than O₂-grown oxide in p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) devices     

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.     

Enhanced reliability for low-temperature gate dielectric of MOS devices by N2O or NO plasma nitridation

Silicon MOS capacitors fabricated solely by low-temperature processes (under 600 °C) are treated with nitridation using N₂O or NO plasma. Their properties are investigated at room temperature under high-field stress. It is found that both kinds of plasmas are effective in improving the gate-oxide hardness against stress-induced damage, which is characterized by a smaller shift in flatband voltage and smaller increase in interface states after the stress. Moreover, NO-nitrided device shows better performance than N₂O-nitrided one. These results show that plasma nitridation has positive effects on the reliability of low-temperature-fabricated devices, which play an important role in flat-panel display systems on glass.     

Plasma charging damage on ultrathin gate oxides

Capacitor C-V and threshold voltage and subthreshold swing of MOSFET's with gate oxide thickness varying from 2.2 to 7.7 nm are analyzed to study the plasma charging damage by the metal etching process. Surprisingly, the ultrathin gate oxide has better immunity to plasma charging damage than the thicker oxide, thanks to the excellent tolerance of the thin gate oxide to tunneling current. This finding has very positive implications for the prospect of manufacturable scaling of gate oxide to very thin thickness     

Effect of the post-gate annealing on the gate reliability of AlGaN/GaN HEMTs

In this paper,we investigated the effect of post-gate annealing (PGA) on reverse gate leakage and the reverse bias reli-ability of Al0.23Ga0.77N/GaN high electron mobility transistors (HEMTs).We found that the Poole-Frenkel (PF) emission is domin-ant in the reverse gate leakage current at the low reverse bias region (Vth ＜ VG ＜ 0 V) for the unannealed and annealed HEMTs.The emission barrier height of HEMT is increased from 0.139 to 0.256 eV after the PGA process,which results in a reduction of the reverse leakage current by more than one order.Besides,the reverse step stress was conducted to study the gate reliabil-ity of both HEMTs.After the stress,the unannealed HEMT shows a higher reverse leakage current due to the permanent dam-age of the Schottky gate.In contrast,the annealed HEMT shows a little change in reverse leakage current.This indicates that the PGA can reduce the reverse gate leakage and improve the gate reliability.     

Synchrotron x-ray irradiation effects on the device characteristics and the resistance to hot-carrier damage of MOSFETs with 4 nm thick gate oxides

The effects of synchrotron x-ray irradiation on the device characteristics and hot-carrier resistance of n- and p-channel metal oxide semiconductor field effect transistors (MOSFETs) with 4 nm thick gate oxides are investigated. In p-channel MOSFETs, device characteristics were significantly affected by the x-ray irradiation but completely recovered after annealing, while the device characteristics in n-channel MOSFETs were not noticeably affected by the irradiation. This difference appears to be due to a difference in interface-state generation. In p-channel MOSFETs, defects caused by boron-ion penetration through the gate oxides may be sensitive to x-ray irradiation, causing the generation of many interface states. These interface states are completely eliminated after annealing in hydrogen gas. The effects of irradiation on the resistance to hot-carrier degradation in annealed 4 nm thick gate-oxide MOSFETs were negligible even at an x-ray dose of 6000 mJ/cm².     

High-field stressing of LPCVD gate oxides

We have investigated gate oxide degradation as a function of high-field constant current stress for two types of oxides, viz. standard dry and LPCVD oxides. Charge injection was done from both electrodes, the gate and the substrate. Our results indicate that compared to dry oxides, LPCVD oxides show reduced charge trapping and interface state generation for inversion stress. The degradation in LPCVD oxides with constant current stress has been explained by the hydrogen model     

Effect of stress voltages on voltage acceleration and lifetime projections for ultra-thin gate oxides

This paper investigates the effect of NFET (N+ poly gate, N+ diffusion of FET) stress voltage conditions, for ultra-thin gate oxides, on the voltage acceleration, and lifetime projections to use conditions. This work employs the model relating the critical defect density (N^BD) to the charge-to-breakdown and the defect generation probability (P_g). The models for N^BD and P_g were adjusted for effects at voltages between 2 V and 3 V, and oxide thickness less than 2.7 nm. For N^BD, a model is proposed that is supported by published data and provides a gradual transition to a plateau for oxide thickness less than 2.7 nm. For P_g, a stronger dependency of Log(P_g) in the range of 2–3 V is employed to give a better fit to published data. This adjusted P_g is also used below 2 V to show trend of projection. In the direct tunneling range below 3 V, there is an increase of the voltage acceleration factor (AF) with decreasing voltage. Also, below 3 V, AF shows a decrease as the oxide thickness is reduced from 2.0 nm to 1.2 nm, and this trend becomes stronger as the gate voltage is reduced. Above a gate stress voltage of 3 V, in the range of 3–4 V, AF is almost constant, and there is a slight decrease of AF with decreasing oxide thickness in the range of 2.0–1.2 nm. A voltage power-law fit for the range above 3 V shows a decreasing power index with decreasing oxide thickness.     

The effects of thermal nitridation conditions on the reliability of thin nitrided oxide films

MIS capacitors on n-type silicon substrate with thin oxide films thermally nitrided in NH3gas ambient at different temperatures and for different times have been fabricated. The effects of nitridation temperature and time on the properties of the thin nitrided oxide films have been examined and analyzed by using a constant current stress. It is found that the oxide films nitrided at 900°C exhibit much improved total charge to breakdown and interface trap generation if proper nitridation time is used. The superior characteristics of the fabricated nitrided oxide films using the proposed optimum conditions are suitable for existing CMOS/VLSI applications.