A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATMswitch based on scalable distributed arbitration

This paper presents the design and implementation of a scalable asynchronous transfer mode switch. We fabricated a 10-Gb/s 4×2 switch large-scale integration (LSI) that uses a new distributed contention control technique that allows the switch LSI to be expanded. The developed contention control is executed in a distributed manner at each switch LSI, and the contention control time does not depend on the number of connected switch LSI's. To increase the LSI throughput and reduce the power consumption, we used 0.25-μm CMOS/SIMOX (separation by implanted oxygen) technology, which enables us to make 221 pseudo-emitter-coupled-logic I/O pins with 1.25-Gb/s throughput. In addition, power consumption of 7 W is achieved by operating the CMOS/SIMOX gates at -2.0 V. This consumption is 36% less than that of bulk CMOS gates (11 W) at the same speed at -2.5 V. Using these switch LSI's, an 8×8 switching multichip module with 80-Gb/s throughput was fabricated with a compact size     

Application of advanced microelectronics to large-scalecommunication equipment-compact and maintenance-free TDMA equipment

An architecture is proposed for TDMA (time division multiple access) equipment and functional-module realization in microelectronics to increase reliability and to reduce hardware size and development time. The approach described basically involves digitization of analog circuits (allowing their realization using digital LSI circuits) and analog IC implementation for high-speed circuits. In order to use general-purpose LSI circuits and ICs, TDMA equipment is reconfigured into a hardware-oriented and simplified architecture. Using this architecture and optimal function assigning to each module, six types of general-purpose synchronization unit LSI circuits have been developed in addition to eleven types of LSI circuits and ICs, i.e. three types of digital LSI circuits, four types of MAICs (monolithic analog ICs), and four types of HICs (hybrid ICs) for a burst modem. As a result of this LSI circuit and IC implementation, the hardware size of TDMA equipment has been reduced to one-fifth of the conventional size, and maintenance-free capability has been achieved     

Practical implementation and packaging technologies for alarge-scale ATM switching system

The practical implementation of a trial large-scale asynchronous transfer mode (ATM) switching system and its packaging technologies are described. The architecture of the ATM switching system is discussed with an emphasis on system scalability. A building block architecture in which switching capacity can be expanded in a modular fashion is introduced. The design of the ATM switching system, including the ATM switch element, is described. The implementation of the VLSIs for the ATM switch which realize a highly modular system is explained. Bit-slice techniques are effectively used to realize a high-speed switch element as a CMOS VLSI chipset. An edge-to-edge orthogonal packaging technique is also presented     

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

Development and performance assessment of a distributedasynchronous protocol for real-time network restoration

The methodology used, and results obtained, in the development and verification of a protocol for real-time network restoration are described. This protocol, called selfhealing, relies on a combination of hardware and software features to achieve an advance in the speed of restoring network spans that have been cut. The hardware environment provides a paradigm for heavily parallel, asynchronous, distributed interaction. This environment is uniquely suited to interactions between digital cross-connect switches (DCS) embedded in a highly-capacity transport network. A speed determination based on an implementation of the protocol exactly as it would exist in the target DCS host machine is given     

80 Gbit/s ATM switch MCM based on multilayer ceramic technology

An 80 Gbit/s asynchronous transfer mode (ATM) switch multichip module (MCM) of dimensions 114×160×6.5 mm has been fabricated. This MCM can support high-density mounting and high-speed interconnection among large-scale-integrated (LSI) chips. Using LSI, ceramic-substrate, high-speed/high-power connector, and compact liquid-cooling technologies, an 80 Gbit/s ATM switching module has been built     

TORUS-switch: a scalable internal speed-up ATM switch architectureand its 5 Gbit/s switch LSI

A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient     

Architecture, performance, and implementation of the tandem banyanfast packet switch

The authors propose a new space-division fast packet switch architecture based on banyan interconnection networks, called the tandem banyan switching fabric (TBSF). It consists of placing banyan networks in tandem, offering multiple paths from each input to each output, thus overcoming in a very simple way the effect of conflicts among packets (to which banyan networks are prone) and achieving output buffering. From a hardware implementation perspective, this architecture is simple in that it consists of several instances of only two VLSI chips, one implementing the banyan network and the other implementing the output buffer function. The basic structure and operation of the tandem banyan switching fabric are described, and its performance is discussed. The authors propose a modification to the basic structure which decreases the hardware complexity of the switch while maintaining its performance. An implementation of the banyan network using a high-performance BiCMOS sea-of-gates on 0.8-μm technology is reported     

A 1.5 Gb/s 8×8 cross-connect switch using a time reservationalgorithm

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s     

Scalable shared-buffering ATM switch with a versatile searchablequeue

The shared-buffering architecture is promising to make a large-scale ATM switch with small buffer size. However, there are two important problems, namely, memory-access speed and complex-control implementation. Advanced 0.5 μm CMOS technology now makes it possible to integrate a huge amount of memory, and enables us to apply more sophisticated architecture than ever before. We propose the funnel-structured expandable architecture with shared multibuffering and the advanced searchable-address queueing scheme for these two problems. The funnel structure gives a flexible capability to build various sizes of ATM switches which are proportional to the number of LSI chips. The searchable-address queue, in which all the addresses of the stored cells for different output ports are queued in a single-FIFO hardware and the earliest address is found by the search function provided inside the queue, can reduce the total memory capacity drastically, and enables the address queue to be contained inside the LSI chip. This technique also has a great advantage for implementing the multicast and multilevel priority-control functions. A 622 Mbit/s 32×8 ATM switch LSI chip set, which consists of a BX-LSI and a CX-LSI, is developed using 0.5 μm pure CMOS technology. By using four chip sets, a 622 Mbit/s 32×32 switch can be installed on one board     

Banyan multipath self-routing ATM switches with shared buffer typeswitch elements

The asynchronous transfer mode (ATM) has been selected as the multiplexing and switching technique for use in the public broadband ISDN (B-ISDN). We propose a large-scale ATM switch architecture in which a banyan multipath self-routing network is combined advantageously with a shared buffer type switch element. The proposed banyan space-division concept yields a simple architecture having the potential to accommodate easily the growth of switch size. Since the interconnection network between switch modules or between switch elements has a twofold banyan architecture, expansion in crosspoints or interconnections with the increase of switch size can be lessened. The multipath self-routing concept makes the switch performance better and leads to an efficient realization of a switch element on a single chip as the fundamental building block of a large-size switch. We analyze the required capacity for queuing buffers in the switching network. The multipath approach inevitably creates information sequence disturbances. Therefore, we also analyze the out-of-sequence phenomenon of a banyan multipath switching system. To satisfy the sequence integrity requirement for ATM, a simple approach is proposed for the multipath switch by using a spacing controller. In addition, we quantify the improvement of out-of-sequence performance under the spacing controller scheme     

A reconfigurable ATM switch fabric for fault tolerance and trafficbalancing

A large-scale asynchronous transfer mode (ATM) switch fabric that can be constructed with currently feasible technology is proposed. Based on analysis of the technology, it is found that module interconnection becomes the bottleneck for a large fast packet switch. Fault tolerance for the switch is achieved by dynamic reconfiguration of the module interconnection network. The design improves system reliability with relatively low hardware overhead. An abstract model of the replacement problem for the design is presented, and the problem is transformed into a well-known assignment problem. The maximum fault tolerance is found, and a fast replacement algorithm is given. The reconfiguration capability can also be used to ameliorate imbalanced traffic flows. The authors formulate this traffic flow assignment problem for the switch fabric and show that the problem is NP-hard. A simple heuristic algorithm is proposed, and an example is given     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

Asynchronous Techniques for System-on-Chip Design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed.     

A redundancy test-time reduction technique in 1-Mbit DRAM with amultibit test mode

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperates with the MBT mode have been introduced. This simple redundancy architecture needs only the RFLG (512 bits for the 1 M×1-bit DRAM) as a hardware option on a memory LSI tester. The program development time for the redundancy test has been shortened. Throughput improvement of six to ten times has been achieved in the actual 1-Mb DRAM redundancy test     

SXmin: a self-routing high-performance ATM packet switch based ongroup-knockout principle

We propose SXmin: a self-routing, group-knockout principle based asynchronous transfer mode (ATM) packet switch which provides comparable delay-throughput performance and packet loss probabilities at significantly reduced hardware requirements compared to earlier switches. The M×N SXmin consists of an N×N Batcher sorter followed by log₂N-1 stages of sort-expander (SX) modules arranged in the form of a complete binary tree. Each SX module consists of a column of 2×2 switches with a wraparound-unshuffle input-output interconnection. This enables the hierarchical utilization of the group-knockout principle to expand the number of inputs by a small factor at each stage, resulting in a significant reduction in overall hardware complexity. Routing at each switch is controlled by a single bit. However, in case of contention, a dual bit resolution algorithm is used locally which drops excess packets in a predetermined manner while ensuring global randomness of packet loss over the entire switching network. There are no internal buffers at the individual stages and therefore the internal delay is constant and proportional to the number of stages. The use of simple hardware components and regular interconnections in the SX modules makes the network suitable for optical implementation     

A new buffer management scheme for hierarchical shared memoryswitches

We study a multistage hierarchical asynchronous transfer mode (ATM) switch in which each switching element has its own local cell buffer memory that is shared among all its output ports. We propose a novel buffer management technique called delayed pushout that combines a pushout mechanism (for sharing memory efficiently among queues within the same switching element) and a backpressure mechanism (for sharing memory across switch stages). The backpressure component has a threshold to restrict the amount of sharing between stages. A synergy emerges when pushout, backpressure, and this threshold are all employed together. Using a computer simulation of the switch under symmetric but bursty traffic, we study delayed pushout as well as several simpler pushout and backpressure schemes under a wide range of loads. At every load level, we find that the delayed pushout scheme has a lower cell loss rate than its competitors. Finally, we show how delayed pushout can be extended to share buffer space between traffic classes with different space priorities     

Design and performance analysis of an asynchronous non-blocking switch with window policy

In this paper, we propose an architecture of an asynchronous non-blocking switch. The switch structure is relatively simple, but it has an advantage in that the window scheme can easily be implemented. Many switch structures synchronized with time slots have been proposed, but they are not efficient when implementing a window scheme. The asynchronous switch proposed in this paper with its implementation of a window scheme can increase its maximum throughput up to 1 in the case of minimum changeover time and large packet size. We also investigate the delay characteristics of the asynchronous switch. In the analysis of delay characteristics, we make some approximations. However, the results of the analysis are in good agreement with simulation results. In addition, the maximum throughput of the switch with finite window size is investigated.     

The hydrogenated amorphous silicon active hollow four quadrantorientation detector for application to neural network imagesensors

The fundamental way to improve the processing speed of pattern recognition is to implement the data processing function by hardware circuits. A simple integrated device by combining hollow four quadrant orientation detector (hollow FOQUOD) with an amorphous silicon thin film transistor as a switch element has been successfully fabricated. This device is called active hollow FOQUOD. The hollow FOQUOD detector can extract the edge position and its orientation from an object image with a precision of 5° which is consistent with the theoretical simulation. It is demonstrated that the thin film transistor can indeed switch the hollow FOQUOD detector on and off and avoid the crosstalk problem when used in a 3×3 two-dimensional array     

A simple and versatile decentralized control for slotted ALOHA,reservation ALOHA, and local area networks

A simple, decentralized control for reducing the delays and stabilizing random-access channels is presented. The control, which is based on a computationally efficient recursive implementation of the minimum mean-squared error (MMSE) predictor of the channel backlog, applies to slotted ALOHA, to reservation ALOHA, and to local area networks (LANs) with carrier-sense multiple access (CSMA) or CSMA with collision detection (CSMA/CD) protocols. The MMSE predictor controller (MMSE-PC) can stabilize the slotted ALOHA for all traffic rates not exceeding e^-1, and it can achieve stable throughput arbitrarily close to one with finite delays in the reservation ALOHA and in LANs. Extensive simulation has shown that the MMSE-PC performs extremely well in all three random-access environments. For the implementation of the MMSE-PC in LANs, synchronization of transmissions is not required but it is required in slotted ALOHA and reservation ALOHA. The MMSE-PC has been implemented in hardware and tested in asynchronous LANs