高性能ZnSnO∶Li/ZnSnO双有源层TFT电学性能的研究

双有源层以迁移率高、开关比高、大面积均匀性好等优点成为近年研究热点。采用射频磁控溅射方法，制备了ZnSnO∶Li/ZnSnO薄膜晶体管(TFT),对其电学特性进行了测试，并研究了器件迁移率提高的原因及其内在的微观机制。研究发现，ZTO∶Li/ZTO TFT表现出了良好的电学特性，其场效应迁移为率为13.98 cm²/(V·s),亚阈值摆幅为0.84 V/dec,开关比为1.13×10⁹。通过XPS对其薄膜进行分析发现，Li的引入导致薄膜中氧和金属结合键的浓度增加，氧空位浓度减少，从而使得TFT的迁移率增大，开关比增大，亚阈值摆幅减小。     

基于In-Zn-Ti-O氧化物半导体材料的薄膜晶体管

在室温下制备了基于In-Zn-Ti-O氧化物半导体的薄膜晶体管,氧化物沟道层中In、Zn、Ti的摩尔比为49∶49∶2。所制备的器件场致迁移率达到9.8cm2/V.s,开关比大于105,亚阈值摆幅0.61V/dec。和未掺Ti器件的比较表明,掺Ti能使器件阈值正向变化,对场致迁移率也有提高作用。     

等离子体处理对非晶IGZO柔性薄膜晶体管性能的影响

本文研究了柔性基板上的薄膜晶体管,使用IGZO作为有源层,栅极绝缘层采用NH3等离子体和N2O等离子体分别进行处理,研究器件性能变化。结果表明等离子体类型及处理时间对阈值电压、场效应迁移率、开关比、亚阈值摆幅（SS）和偏压稳定性都有影响。TFT器件用NH3等离子体处理10秒显示出最佳的器件性能,阈值电压达到0.34 V,场效应迁移率为15.97 cm2/Vs,开关比为6.33×107,亚阈值摆幅为0.36 V /dec。本文提出的柔性IGZO-TFT是下一代柔性显示驱动装置较好选择。     

KH550-GO复合栅介质低压氧化物薄膜晶体管

采用旋涂法制备硅烷偶联剂-氧化石墨烯(KH550-GO)新型复合栅介质薄膜,由于栅介质层和沟道层界面处明显的双电层效应,单位面积电容高达2.18×10~(–6)F/cm~2。通过自组装法,借助磁控溅射仪,仅需一次掩膜,即可同时生成晶体管的沟道与源漏电极。利用半导体参数分析仪在室温黑暗的条件下测量该晶体管的电学特性,结果表明,KH550-GO栅介质氧化物薄膜晶体管具有优良的电学性能,其工作电压仅为2 V、饱和电流为580μA、亚阈值摆幅108 m V/dec、开关比4×10~7、场效应迁移率16.7 cm~2·V~(-1)·s~(-1)。     

基于FET结构的MoS2器件的研究进展

对带隙可调的二维层状半导体二硫化钼(MoS2)的材料特性以及基于MoS2薄膜的器件性能和应用进行了简单阐述,重点分析了多种MoS2场效应晶体管(FET)的结构特点,并对MoS2 FET的制备工艺、电学性能(载流子迁移率、电流开关比、亚阈值摆幅等)以及栅极介质层材料对器件性能的影响等进行了综述.在此基础上进一步总结了近年...     

溶液法制程对有机薄膜晶体管性能影响的研究

基于新型的聚合物绝缘材料和半导体材料,采用溶液法旋涂工艺制作有机薄膜晶体管,通过优化聚合物半导体材料的溶剂、旋涂速度、退火温度等条件,提高有机薄膜晶体管的器件性能。结果表明,不同溶剂溶解半导体对制成的有机薄膜晶体管的迁移率影响明显;半导体层旋涂速度过慢和退火温度过低都会降低有机薄膜晶体管的性能。当采用1,2,4-三氯苯(TCB)作为半导体溶剂,旋涂速度为3 000r/min,后烘温度为190℃时,有机薄膜晶体管的迁移率可以达到约0.5cm2·V-1·s-1,亚阈值摆幅降至约0.6V/dec,开关比大于106。     

氧分压对射频溅射制备ZTO沟道层的薄膜晶体管器件性能的影响

以锌锡氧化物(ZTO)薄膜作为沟道层,聚甲基丙烯酸甲酯(PMMA)薄膜作为介质层低温(100℃)制备了顶栅共面结构的薄膜晶体管(TFT),并研究了ZTO沟道层成膜过程中氧分压对器件性能的影响。结果表明,ZTO沟道层具有稳定的非晶结构、较高的可见光透明性(在400~700nm范围内平均透过率大于等于89.61%),且增大氧分压有利于其可见光透明性的提升。霍尔测试结果表明,增大氧分压(由3.5×10-2Pa增大到7.5×10-2Pa)会降低ZTO电子载流子浓度(由4.73×10¹⁵cm-3降低到6.11×10¹²cm-3),致使基于ZTO沟道层TFT器件的能耗降低(表现为关态电流的降低和耗尽型器件阈值电压的正向移动)。此外,增大氧分压还有益于沟道层/介质层界面状态的优化,即亚阈值摆幅减小。     

栅宽对AlGaN/GaN HEMTs亚阈值摆幅的影响

制备了不同栅极宽度的AlGaN/GaN高电子迁移率晶体管，通过测量各器件电容-电压曲线和转移特性曲线，得到了栅沟道载流子输运特性以及亚阈值摆幅，结果显示当栅极宽度从10μm增加到50μm时，亚阈值摆幅下降了40.3%.定性且定量地分析了亚阈值摆幅值随栅极宽度变化的原因，发现不同的栅极宽度对应不同的极化散射强度，亚阈值摆幅的变化是由栅沟道载流子输运特性和极化散射效应造成的.为AlGaN/GaN高电子迁移率晶体管开关性能优化提供了新的视角与维度，将促进其更好地应用于无线通信、电力传输以及国防军工领域.     

基板温度对氧化锌薄膜晶体管性能的影响

以ITO玻璃为衬底,利用射频磁控溅射制备了以氧化硅为绝缘层的氧化锌薄膜晶体管。研究了氧化锌薄膜制备过程中不同的衬底温度（衬底温度分别为室温、100℃ 和200℃）对于器件性能的影响。和室温下制备的氧化锌薄膜晶体管相比,衬底温度200℃条件下制备的器件的场效应迁移率提高了94% （从1.6cm2/Vs 提高至3.11cm2/Vs）,亚阈值摆幅 从2.5V/dec 降低至1.9 V/dec 而且阈值电压漂移也从18V 减小至3V （老化电压为25V的正栅压,老化时间为1小时）。实验结果表明,衬底加热对于氧化锌薄膜晶体管的迁移率、亚阈值摆幅和偏压稳定性有明显的影响。利用原子力显微镜AFM对氧化锌薄膜的特性就行了研究,器件性能提高的原因也在文中进行了阐述。     

顶栅共面结构非晶氧化物薄膜晶体管的低成本制备及性能研究

将溶液法制备的不含镓的非晶InAlZnO薄膜和有机聚甲基丙烯酸甲酯薄膜分别作为沟道层和介质层,制备了顶栅共面结构的非晶氧化物薄膜晶体管(TFT)器件,探讨了沟道层中Al含量对器件性能的影响。结果表明：Al对InZnO薄膜中氧空位的形成能起到一定抑制作用,增加Al含量即可降低沟道层中的电子载流子浓度,使得InAlZnO TFT器件阈值电压正向移动、关态电流减小,以有利于器件开关比的提升。此外,基于沟道层中Al含量的调整可通过优化沟道层/介质层界面状态来促进器件阈值电压滞回稳定性的提升。当沟道层中Al含量为30%时,制备的器件具有最佳综合性能。     

Transparent Oxide Thin-Film Transistors Composed of Al and Sn-doped Zinc Indium Oxide

We have fabricated the transparent bottom gate thin-film transistors (TFTs) using Al and Sn-doped zinc indium oxide (AT-ZIO) as an active layer. The AT-ZIO active layer was deposited by RF magnetron sputtering at room temperature, and the AT-ZIO TFT showed a field effect mobility of 15.6 $ hbox{cm}^{2}/hbox{Vs}$ even before annealing. The mobility increased with increasing the $hbox{In}_{2}hbox{O}_{3}$ content and postannealing temperature up to 250 $^{circ}hbox{C}$. The AT-ZIO TFT exhibited a field effect mobility of 30.2 $hbox{cm}^{2}/hbox{Vs}$, a subthreshold swing of 0.17 V/dec, and an on/off current ratio of more than $10^{9}$ .      

Heat stress exposing performance of deep-nano HK/MG nMOSFETs using DPN or PDA treatment

Decoupled plasma nitridation (DPN) or post-deposition annealing (PDA) process after high-k (HK) deposition to repair the bulk traps or the oxygen vacancy in gate dielectric is an impressive choice to raise up the device performance. Before heat stress, the electrical performance in drive current, channel mobility and subthreshold swing with both treatments was approximate, except the higher annealing atmosphere causing the thicker interfacial layer and reducing the overall related dielectric constant. After temperature stress, the electrical performance for all of the tested devices was slightly deteriorated. The degradation degree for electrical performance with PDA treatment group was the worst case due to NH₃ atmosphere forming Si–H bond on the channel surface, which was broken after stress and produced more interface state reflected with the increase of subthreshold swing.     

Amorphous-silicon thin-film transistors with very high field-effectmobility

The fabrication and performance of hydrogenated amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with field-effect mobilities of 5.1 cm²/V-s are discussed. This is the highest field-effect mobility of this type of TFT reported to date. The device shows an on/off current ratio exceeding 10⁵ and a subthreshold swing of 0.5 V/decade     

The effects of H2-O2-plasma treatment on thecharacteristics of polysilicon thin-film transistors

The effects of H₂-plasma followed by O₂-plasma treatment on n-channel polysilicon thin-film transistors (TFTs) were investigated. It was found that the H₂-O₂-plasma treatment is more effective in passivating the trap states of polysilicon films than the H₂-plasma or O₂-plasma treatment only. Hence, it is more effective in improving the device performance with regard to subthreshold swing, carrier mobility, and the current ON/OFF ratio. It is also found that thermal annealing of plasma-treated devices increases the deep states but has no effect on the tail states of the devices     

Pentacene TFT with improved linear region characteristics usingchemically modified source and drain electrodes

We have fabricated pentacene active layer organic thin film transistors (OTFTs) using chemically-modified source and drain contacts with improved contact and linear region characteristics. OTFTs fabricated on heavily doped, thermally oxidized single-crystal silicon substrates have linear field-effect mobility greater than 0.5 cm² /V-s at a drain-source voltage of -0.1 V, on/off current ratio greater than 10⁷, and subthreshold slope as low as 0.7 V/decade     

Influence of substrate temperature on the performance of zinc oxide thin film transistor

Top-contact thin film transistors（TFTs） using radio frequency（RP） magnetron sputtering zinc oxide （ZnO） and silicon dioxide（SiO₂） films as the active channel layer and gate insulator layer,respectively,were fabricated.The performances of ZnO TFTs with different ZnO film deposition temperatures（room temperature, 100℃and 200℃） were investigated.Compared with the transistor with room-temperature deposited ZnO films, the mobility of the device fabricated at 200℃is improved by 94%and the threshold voltage shift is reduced from 18 to 3 V（after 1 h positive gate voltage stress）.Experimental results indicate that substrate temperature plays an important role in enhancing the field effect mobility,sharping the subthreshold swing and improving the bias stability of the devices.Atomic force microscopy was used to investigate the ZnO film properties.The reasons for the device performance improvement are discussed.     

Study on hydrogenation of polysilicon thin film transistors by ionimplantation

Hydrogenation of polysilicon (poly-Si) thin film transistors (TFT's) by ion implantation has been systematically studied. Poly-Si TFT performance was dramatically improved by hydrogen ion implantation followed by a forming gas anneal (FGA). The threshold voltage, channel mobility, subthreshold swing, leakage current, and ON/OFF current ratio have been studied as functions of ion implantation dose and FGA temperature. Under the optimized conditions (H⁺ dose of 5×10¹⁵ cm^-2 and FGA temperature at 375°C), NMOS poly-Si TFT's fabricated by a low temperature 600°C process have a mobility of ~27 cm ²/V·s, a threshold voltage of ~2 V, a subthreshold swing of ~0.9 V/decade, and an OFF-state leakage current of ~7 pA/μm at V_DS=10 V. The avalanche induced kink effect was found to be reduced after hydrogenation     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

溅射法制备钇掺杂铟锌氧薄膜和器件特性研究王丹丹,王卿璞*,王汉斌,张锡健,武丽伟,李福杰,袁帅中国,济南,山东大学物理学院

室温下,采用射频磁控溅射法分别在钠钙玻璃和P型硅衬底上制备了不同厚度的钇掺杂铟锌氧薄膜。研究了薄膜的结构形貌和光学特性。以P型硅为栅极制备了底栅结构的YIZO薄膜晶体管,并研究了器件的输出和转移特性。研究发现,室温下制备的所有Y掺杂IZO薄膜均为非晶结构,YIZO薄膜晶体管均为n沟道耗尽型器件。有源层厚度为20nm的器件的开关电流比超过105,亚阈值摆幅为2.20 V/decade,阈值电压为-1.0V, 饱和迁移率为0.57 cm2/ V·s。     

Thin-film transistors on plastic and glass substrates using silicon deposited by microwave plasma ECR-CVD

Thin-film transistors (TFTs) were fabricated on polyimide and glass substrates at low temperatures using microwave ECR-CVD deposited amorphous and nanocrystalline silicon as active layers. The amorphous Si TFT fabricated at 200 /spl deg/C on the polyimide foil had a saturation region field effect mobility of 4.5 cm/sup 2//V-s, a linear region mobility of 5.1 cm/sup 2//V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/decade, and an ON/OFF current ratio of 7.9 /spl times/ 10/sup 6/. This large mobility and high ON/OFF current ratio were attributed to the high-quality channel materials with less dangling bond defect states. Nanocrystalline Si TFTs fabricated on glass substrates at 400 /spl deg/C showed a saturation region mobility of 14.1 cm/sup 2//V-s, a linear region mobility of 15.3 cm/sup 2//V-s, a threshold voltage of 3.6 V, and an ON/OFF current ratio of 6.7 /spl times/ 10/sup 6/. TFT performance was mostly independent of substrate type when fabrication conditions were the same.