新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

热载流子诱生MOSFET/SOI界面陷阱的正向栅控二极管技术表征

本文完成了热载流子诱生MOSFET/SOI界面陷阱正向栅控二极管技术表征的实验研究 .正向栅控二极管技术简单、准确 ,可以直接测得热载流子诱生的平均界面陷阱密度 ,从而表征器件的抗热载流子特性 .实验结果表明 :通过体接触方式测得的MOSFET/SOI栅控二极管R G电流峰可以直接给出诱生的界面陷阱密度 .抽取出来的热载流子诱生界面陷阱密度与累积应力时间呈幂指数关系 ,指数因子约为 0 787     

热载流子诱生MOSFET／SOI界面陷阱的正向机控二极管技术表征

本文完成了热载流子诱生MOSFET/SOI界面陷阱正向栅控二极管技术表征的实验研究。正向栅控二极管技术简单、准确，可以直接测得热载流子诱生的平均界面陷阱密度，从而表征器件的抗热载流子特性。实验结果表明：通过体接触方式测得的MOSFET/SOI栅控二级管R-G电流峰可以直接给出诱生的界面陷阱密度。抽取出来的热载流子诱生界面陷阱密度与累积应力时间呈幂指数关系，指数因子约为0.787。     

正向栅控二极管监测F-N电应力诱生的SOI-MOSFET界面陷阱

报道了正向栅控二极管R-G电流法表征F-N电应力诱生的SOI-MOSFET界面陷阱的实验及其结果．通过体接触的方式实现了实验要求的SOI-MOSFET栅控二极管结构．对于逐渐上升的累积应力时间,测量的栅控二极管电流显示出明显增加的R-G电流峰值．根据SRH理论的相关公式,抽取出来的诱生界面陷阱密度是随累积应力时间的上升而呈幂指数的方式增加,指数为0.4.这一实验结果与文献先前报道的基本一致．     

正向栅控二极管监测F- N电应力诱生的SOI- MOSFET界面陷阱

报道了正向栅控二极管 R- G电流法表征 F- N电应力诱生的 SOI- MOSFET界面陷阱的实验及其结果 .通过体接触的方式实现了实验要求的 SOI- MOSFET栅控二极管结构 .对于逐渐上升的累积应力时间 ,测量的栅控二极管电流显示出明显增加的 R- G电流峰值 .根据 SRH理论的相关公式 ,抽取出来的诱生界面陷阱密度是随累积应力时间的上升而呈幂指数的方式增加 ,指数为 0 .4.这一实验结果与文献先前报道的基本一致     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对pMOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于pMOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是pMOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对p MOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于p MOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是p MOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

线性余因子差分亚阈电压峰技术测量电应力诱生MOSFET界面陷阱的研究

本文提出了用线性余因子差分亚阈电压峰测量电应力诱生MOSFET界面陷阱的新技术并进行了实验验证 .详细介绍了该方法的基本原理和实验实现 ,得到了电应力诱生MOSFET界面陷阱和累积应力时间的关系 .该方法具有普适性 ,可用于MOSFET的一般可靠性研究和寿命预测 .     

线性余因子差分亚阀电压峰技术测量电应力诱生MOSFET界面陷阱的研究

本文提出了用线性余因子差分亚阀电压峰测量电应力诱生MOSFET界面陷阱的新技术并进行了实验验证，详细介绍了该方法的基本原理和实验实现，得到了电应力诱生MOSFET界面陷阱和累积应力时间的关系，该方法具有普适性，可用于MOSEFT的一般可靠性研究和寿命预测。     

正向栅控二极管的R-G电流直接表征NMOSFET

使用半导体器件数值分析工具DESSISE-ISE,对正向栅控二极管R-G电流表征NMOSFET沟道pocket或halo注入区进行了详尽的研究.数值分析表明:由于栅控正向二极管界面态R-G电流的特征,沟道工程pocket或halo注入区的界面态会产生一个独立于本征沟道界面态R-G电流特征峰的附加特征峰.该峰的幅度对应于pocket或halo区的界面态大小,而其峰位置对应于pocket或halo区的有效表面浓度.数值分析还进一步显示了该附加特征峰的幅度对pocket或halo 区的界面态变化的敏感性和该峰的位置对pocket或halo区的有效表面浓度变化的敏感性.根据提出的简单表达式,可以用实验得到的R-G电流的特征直接抽取沟道工程的pocket或halo注入区的界面态和有效表面浓度.     

Hot carrier induced degradation in mesa-isolated n-channel SOIMOSFETs operating in a Bi-MOS mode

A thorough investigation of hot carrier effects is made in mesa-isolated SOI nMOSFETs operating in the Bi-MOS mode (abbreviated as Bi-nMOSFETs). As a result of its unique hybrid operation mechanism, significant reduction of hot carrier induced maximum transconductance degradation and threshold voltage shift in the Bi-nMOSFET is observed in comparison with that in the conventional SOI nMOSFETs. Device lifetime of SOI Bi-nMOSFETs and conventional SOI nMOSFETs was roughly estimated for comparison. In view of the analysis of the degradation mechanism, the devices were stressed under different conditions. The post-stress body current and stress body current in Bi-nMOSFETs as a function of the stress time and stress drain voltage were evaluated as further proofs of the aging reasons. The hot electron injection is found to be the dominant degradation process in the SOI Bi-nMOSFETs. Compared with SOI nMOSFETs, SOI Bi-nMOSFETs show better immunity to the parasitic bipolar transistor action due to the body contact. In addition, the positive body bias can result in lowered hot hole injection into the gate oxide due to the provision of the generated hole leakage path, and thus decreased interface traps     

Reliability of advanced high-k/metal-gate n-FET devices

Hot-carrier degradation and bias-temperature instability of FinFET and fully-depleted SOI devices with high-k gate dielectrics and metal gates are investigated. Thinner SOI results in increased hot-carrier degradation, which can be recovered by junction engineering. FinFETs with (1 1 0) Si active surfaces exhibit degradation of sub-threshold swing after hot carrier stress, indicating generation of interface states. The effect of duty cycle on bias-temperature instability modulates the quasi-steady-state trap occupancy over a broad distribution of electron trapping and de-trapping times. Only the deeper traps remain filled for low duty cycle, and shallower traps are emptied during AC stress.     

FORWARD GATED—DIODE METHOD FOR DIRECTLY MEASURING STRESS—INDUCED INTERFACE TRAPS IN NMOSFET／SOI

Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter.This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device‘s hot carrier characteristics.For the tested device, an expected power law relationship of Δnit-t^0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.     

Impact of latch phenomenon on low-frequency noise in SOI MOSFETs

The low-frequency noise in fully (FD) and partially (PD) depleted SOI MOSFETs is experimentally investigated for channel lengths down to 0.1 μm. The noise is discussed in terms of carrier number and mobility fluctuations for a wide range of SOI structures. Furthermore, the influence of the latch effect on low-frequency noise is analyzed. It is found that the flicker noise is mainly caused by the carrier number fluctuations due to the dynamic trapping of electrons (or holes) by oxide interface traps in all the SOI devices. However, an excess noise is also obtained in the presence of a parasitic bipolar action.     

Comparative analysis of hot electron injection and induced devicedegradation in scaled 0.1 μm SOI n-MOSFETs using Monte Carlosimulation

A self-consistent Monte Carlo (MC) simulator is employed to investigate and compare hot electron phenomena in three competing design strategies for 0.1 μm SOI n-MOSFETs operating under low voltage conditions, i.e., V_d considerably less than the Si-SiO₂ injection barrier height φ_b. Simulations of these designs reveal that non-local carrier transport effects and two-dimensional current how play a significant role in determining the relative rate and location of hot electron injection into both the front and back oxides. Specifically, simulations indicate that electron-electron interactions near the drain edge are a main source of electron energies exceeding φ_b. The hot electron injection distributions are then coupled with an empirical model to generate interface state distributions at both the front and back oxide interfaces. These interface states are incorporated into a drift-diffusion simulator to examine relative hot-electron-induced device degradation for the three 0.1 μm SOI designs. Simulations suggest that both the Si layer thickness and doping distribution affect device sensitivity to hot-electron-induced interface states. In particular, the simulations show that a decrease in the channel doping results in increased sensitivity to back oxide charge. In the comparison of the heavily-doped designs, the design with a thinner T_Si experiences significantly more hot-electron-induced oxide damage in the back oxide and more degradation from the charged states at the back interface     

Donor-like interface trap generation in pMOSFET's at roomtemperature

The generation of donor-like interface traps under room temperature bias stress is observed. This generation process is insensitive to the gate polarity, hot carrier stress, and positive charge formation in the gate oxide. It requires the simultaneous presence of boron- and water-related species. The generated interface traps are nonuniformly distributed along the channel     

Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET’s (n-DTMOSFET) measured by gated-diode configuration

In this paper the hot carrier degradation behavior of the SOI dynamic-threshold-voltage nMOSFET’s (n-DTMOSFET’s) is investigated based on the forward gated-diode configuration. With peak diode current as an indicator, the hot carrier induced degradation of SOI n-DTMOSFET’s is compared with the corresponding SOI nMOSFET’s. Due to the connection of the gate and the body and thus the positive-biased source–body and drain–body junction, the SOI n-DTMOSFET’s exhibit lower peak diode current than the conventional counterparts, showing smaller generated defect density and thus lower hot carrier induced degradation. The generated defect distribution in SOI n-DTMOSFET is analyzed. It is shown that despite of the tied gate-body, the peak of the generated defect density tends to lie in the gate-to-drain overlap region. The defect distribution exerts different influences on the diode current of the long channel device and short channel device with different electric field. Moreover, even with the positive biased body, the generated defects in SOI DTMOSFT are more apt to flow to front interface rather than back interface, resulting in the more severe degradation of the front interface in SOI n-DTMOSFET’s. This gives the main flow direction of the generated defects.     

Numerical Analysis of Characterized Back Interface Traps of SOI Devices by R-G Current

Characterized back interface traps of SOI devices by the Recombination-Generation (R-G) curren: has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSiS-ISE. The basis of the principle for the R-G current's characterizing the back interface traps of SOI lateral p+p-n+ diode has been demonstrated. The dependence of R-G cur rent on interface trap characteristics has been examined, such as the state density, surface recombination velocity and the trap energy level. The R-G current proves to be an effective tool for monitoring the back interface of SOI devices.     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET''''S

The hot-carrier-induced oxide regions in the front and back interfaces are systemati-cally studied for partially depleted SOI MOSFET's. The gate oxide properties are investigated forchannel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stressexperiments with three typical hot-carrier injection, i.e., the maximum gate current, maximumsubstrate current and parasitic bipolar transistor action. Experiments show that PMOSFET's     

栅控二极管R-G电流法表征SOI-MOS器件埋氧层界面陷阱的敏感性分析

通过数值模拟手段 ,用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对 R- G电流大小的影响规律 .结果表明 :无论在 FD还是在 PD SOI MOS器件中 ,界面陷阱密度是决定 R- G电流峰值的主要因素 ,硅膜厚度和沟道掺杂浓度的影响却因器件的类型而异 .为了精确地用 R- G电流峰值确定界面陷阱的大小 ,器件参数的影响也必须包括在模型之中