用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

一种应用于DRM/DAB调谐器的低噪声及dB线性中频可变增益放大器设计

A broadband CMOS intermediate frequency （IF） variable-gain amplifier （VGA） for DRM/DAB tuners is presented. The VGA comprises two cascaded stages： one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18μm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of-10 to 18 dB. It can operate in the frequency range of 30-700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is -3.9 dBm.     

A digital input class-D audio amplifier with sixth-order PWM

A digital input class-D audio amplifier with a sixth-order pulse-width modulation(PWM)modulator is presented.This modulator moves the PWM generator into the closed sigma–delta modulator loop.The noise and distortions generated at the PWM generator module are suppressed by the high gain of the forward loop of the sigma–delta modulator.Therefore,at the output of the modulator,a very clean PWM signal is acquired for driving the power stage of the class-D amplifier.A sixth-order modulator is designed to balance the performance and the system clock speed.Fabricated in standard 0.18 m CMOS technology,this class-D amplifier achieves 110 dB dynamic range,100 dB signal-to-noise rate,and 0.0056%total harmonic distortion plus noise.     

A high-performance low-power CMOS AGC for GPS application

In this paper, a wide tuning range, low power CMOS automatic gain control (AGC) with a simple architecture is proposed. The proposed AGC is composed of variable gain amplifier (VGA), comparator and charge pump, and the dB-linear gain is controlled by charge pump. The AGC was implemented in a 0.18um CMOS technology. The dynamic range of the VGA is more than 55dB, the bandwidth is 30MHz and the gain error lower than ±1.5dB over the full temperature and gain ranges. It is designed for GPS application and is fed from a single 1.8V power supply. The AGC power consumption is less than 5mW and area of the AGC is 700*450um2.     

A process/temperature variation tolerant RSSI

A low power process/temperature variation tolerant CMOS received signal strength indicator (RSSI) and limiter amplifier are designed using SMIC 0.13μm CMOS technology. The limiter uses six-stage amplifier architecture for minimum power consideration. The RSSI has a dynamic range more than 60dB, and the RSSI linearity error is within ±0.5dB for an input power from -65dBm to -8dBm. The RSSI output voltage is from 0.15V to 1V and the slope of the curve is 14.17mV/dB. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics. The RSSI with integrated AGC loop draws 1.5mA (I and Q paths) from a 1.2V single supply.     

X 波段氮化镓合成固态放大器

Based on a self-developed A1GaN/GaN HEMT with 2.5 mm gate width technology on a SiC substrate, an X-band GaN combined solid-state power amplifier module is fabricated. The module consists of an AIGaN/GaN HEMT, Wilkinson power couplers, DC-bias circuit and microstrip line. For each amplifier, we use a bipolar DC power source. Special RC networks at the input and output and a resistor between the DC power source and the gate of the transistor at the input are used for cancellation of self-oscillation and crosstalk of low-frequency of each amplifier. At the same time, branches of length 3λ/4 for Wilkinson power couplers are designed for the elimination of self-oscillation of the two amplifiers. Microstrip stub lines are used for input matching and output matching. Under Vds = 27 V, Vgs = -4.0 V, CW operating conditions at 8 GHz, the amplifier module exhibits a line gain of 5.6 dB with power added efficiency of 23.4%, and output power of 41.46 dBm （14 W）, and the power gain compression is 3 dB. Between 8 and 8.5 GHz, the variation of output power is less than 1.5 dB.     

一种集成二进制权精确对数线性可编程增益放大器的卫星导航接收机数字自动增益控制环路

A novel digitally controlled automatic gain control(AGC) loop circuitry for the global navigation satellite system(GNSS) receiver chip is presented. The entire AGC loop contains a programmable gain amplifier(PGA),an AGC circuit and an analog-to-digital converter(ADC), which is implemented in a 0.18 m complementary metal–oxide–semiconductor(CMOS) process and measured. A binary-weighted approach is proposed in the PGA to achieve wide d B-linear gain control with small gain error. With binary-weighted cascaded amplifiers for coarse gain control, and parallel binary-weighted trans-conductance amplifier array for fine gain control, the PGA can provide a 64 dB dynamic range from4 to 60 dB in 1.14 dB gain steps with a less than 0.15 dB gain error. Based on the Gaussian noise statistic characteristic of the GNSS signal, a digital AGC circuit is also proposed with low area and fast settling. The feed-backward AGC loop occupies an area of 0.27 mm2 and settles within less than165 s while consuming an average current of 1.92 mA at 1.8 V.     

A wideband RF amplifier for satellite tuners

This paper presents the design and measured performance of a wideband amplifier for a direct conversion satellite tuner.It is composed of a wideband low noise amplifier(LNA) and a two-stage RF variable gain amplifier(VGA) with linear gain in dB and temperature compensation schemes.To meet the system linearity requirement, an improved distortion compensation technique and a bypass mode are applied on the LNA to deal with the large input signal.Wideband matching is achieved by resistive feedback and an off-chip LC-ladder matching network.A large gain control range(over 80 dB) is achieved by the VGA with process voltage and temperature compensation and dB linearization.In total,the amplifier consumes up to 26 mA current from a 3.3 V power supply. It is fabricated in a 0.35-μm SiGe BiCMOS technology and occupies a silicon area of 0.25 mm~2.     

A 14-bit 40-MHz analog front end for CCD application

A 14-bit, 40-MHz analog front end (AFE) for CCD scanners is analyzed and designed. The proposed system incorporates a digitally controlled wideband variable gain amplifier (VGA) with nearly 42 dB gain range, a correlated double sampler (CDS) with programmable gain functionality, a 14-bit analog-to-digital converter and a programmable timing core. To achieve the maximum dynamic range, the VGA proposed here can linearly amplify the input signal in a gain range from -1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth. A novel CDS takes image information out of noise, and further amplifies the signal accurately in a gain range from 0 to 18 dB in 0.035 dB step. A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity. An internal timing core can provide flexible timing for CCD arrays, CDS and ADC. The proposed AFE was fabricated in SMIC 0.18 μm CMOS process. The whole circuit occupied an active area of 2.8×4.8 mm² and consumed 360 mW. When the frequency of input signal is 6.069 MHz, and the sampling frequency is 40 MHz, the signal to noise and distortion (SNDR) is 70.3 dB, the effective number of bits is 11.39 bit.     

A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier （LNA） and a passive mixer with no external balun for near-zero-IF （Intermediate Frequency）/RF （Radio Frequency） applications are described. The LNA, fabricated in the 0.18μm 1P6M CMOS technology, adopts a gain-switched technique to increase the linearity and enlarge the dynamic range. The mixer is an IQ-based passive topology. Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω. Combining LNA and mixer, the front-end measured performances in high gain state are： -15dB of Sll, 18.5dB of voltage gain, 4.6dB of noise figure, 15dBm of IIP3, 85dBm to -10dBm dynamic range. The full circuit drains 6mA from a 1.8V supply.     

A low-noise BiCMOS amplifier channel for telecommunications

A low-noise low-pass amplifier channel designed for telecommunications is described. The channel has an 80-kHz corner frequency and total dynamic range of 94 dB. To achieve the high dynamic range, the amplifier channel is constructed with a BiCMOS process and a relative high supply voltage of ±8V is used. To further increase the dynamic range, the baseband amplifier has two branches, a low gain (A = 29 dB) and a high gain (A = 73 dB) branch, comprising a common continuous-time preamplifier and separate antialias filters, switchedcapacitor filters, and postamplifiers. Differential signal processing is used to reduce the effect of common-mode disturbances.     

雷达中频放大器的线性对数双特性设计

雷达数字中频接收机需要一个线性中频预放大电路和一个监测用的对数中频放大器。采用射频变压器形成输入匹配网络,采用高性能低噪声宽带差分放大器AD8350作为线性放大器件,采用双调谐回路作为选频网络,采用魔T电路构成功率分配网络,采用高动态范围宽带对数放大器AD8309作为对数放大器件,设计了一个兼具线性和对数特性的中频放大器。实验表明,该放大器中频输入输出阻抗50Ω,中心频率30 MHz,带宽4 MHz。线性通道增益为18 dB,输出动态范围达98 dB(1 dB压缩点-90 dBm和+8 dBm)。对数通道中,在输入功率为-68 dBm～-8 dBm时,对数放大器输出电压范围对应为0.19 V～2.06 V。     

一款适用于WCDMA标准的大动态范围SiGe HBT可变增益放大器设计

第三代移动通信标准WCDMA要求放大器增益可调,并且增益动态范围较大.根据这一要求给出了一种基于SiGe HBT具有高动态范围的可变增益放大器(VGA)设计.放大器为三级级联结构,第一级为输入缓冲级,第二级为增益控制级,最后为放大级.VGA的增益控制通过调整第二级的偏置实现.VGA在1.95 GHz频率下,在0～2.7 V增益控制电压变化下,具有44 dB增益变化范围,最大增益49 dB.在最大增益处最小噪声系数为2.584 dB,输入输出电压驻波比低于2,性能良好.     

一种71dB动态范围的低功耗可编程增益放大器

本文实现了一款应用于电力线通信的可编程增益放大器(PGA)。采用闭环直接耦合方式,动态范围为71dB,调节精度为1dB。为了优化功耗和面积,本文提出了一种新的电阻阵列。该设计在SMIC0.18μm工艺下仿真,结果表明:在35dB增益下输入参考噪声为20nV/姨Hz;输出电压峰峰值为1V时,THD达到-68dB;最大增益误差为0.11dB;在1.8V的供电电压下,功耗为1mA。     

毫米波大动态宽带单片低噪声放大器

利用0.25μmGaAsPHEMT低噪声工艺,设计并制造了2种毫米波大动态宽带单片低噪声放大器。第1种为低增益大动态低噪声放大器,单电源+5V工作,测得在26～40GHz范围内,增益G=10±0.5dB,噪声系数NF≤2.2dB,1分贝压缩点输出功率P1dB≥15dBm;第2种为低压大动态低噪声放大器,工作电压为3.6V,静态电流0.6A(输出功率饱和时,动态直流电流约为0.9A),在28～35GHz范围内,测得增益G=14～17dB,噪声系数约4.0dB,1分贝压缩点输出功率P1dB≥24.5dBm,最大饱和输出功率≥26.8dBm,附加效率约10%～13.6%。结果中还给出了2种放大器直接级联的情况。     

一种用于生物信号采集的CMOS全差分前置跨阻放大器设计

针对生物信号微弱、变化范围大等特点设计了一种用于检测微弱电流的全差分跨阻放大器(TIA)电路结构。不同于传统电路的单端输入,该结构采用高增益的全差分两级放大器实现小信号输入及轨到轨输出。基于CSMC 0.18μm CMOS工艺,采用1.8V电源电压对设计的电路进行了仿真,仿真结果表明:TIA输入电流动态范围为100nA^10μA,最大跨阻增益达到104.38dBΩ,-3dB带宽为4MHz,等效输入噪声电流为1.26pA/Hz。对电路进行跨阻动态特性仿真表明,在输入电流为100nA时,输出电压的动态摆幅达到3.24mV,功耗仅为250μW,总谐波失真(THD)为-49.93dB。所设计的高增益、低功耗、宽输入动态范围TIA适用于生物医疗中极微小生物信号的采集,可作为模块电路集成在便携设备中。     

5.7 GHz low-power variable-gain LNA in 0.18 /spl mu/m CMOS

A variable-gain low-noise amplifier (LNA) suitable for low-voltage and low-power operation is designed and implemented in a standard 0.18 /spl mu/m CMOS technology. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7 GHz LNA exhibits 16.4 dB gain, 3.5 dB noise figure and 8 dB gain tuning range with good input and output return losses. The LNA consumes 3.2 mW DC power from a supply voltage of 1 V. A gain/power quotient of 5.12 dB/mW is achieved in this work.     

一种-16 dB ~12 dB增益范围的高线性度PGA设计

可编程增益放大器广泛应用于射频接收通道,起中频放大、驱动模数转换器的功能.基于电阻反馈运放设计的可编程增益放大器具有动态范围大、线性度高的特点.文中采用互补金属氧化物半导体工艺设计实现了一种基于全差分运放和衰减器的宽范围、高线性度可编程增益放大器.测试结果表明增益变化范围为-16dB～12dB,步进为1 dB,输出1 dB压缩点大于10 dBm@60 MHz,输出三阶交调点大于26 dBm@60 MHz.     

Bipolar monolithic amplifiers for a gigabit optical repeater

Main amplifier, AGC amplifier, and preamplifier ICs have been designed and fabricated using an advanced silicon bipolar process to provide the required characteristics of repeater circuits for a gigabit optical fiber transmission system. The bipolar technology used involved a separation width of 0.3 /spl mu/m between the emitter and the base electrode. New circuit techniques were also used. The differential type main amplifier has a peaking function which can be varied widely by means of DC voltage supplied at the outside IC terminal. A bandwidth which can be varied to about three times the value for a nonpeaking amplifier is easily obtained. The gain and maximum 3-dB down bandwidth were 4 dB and 4 GHz, respectively. The main feature of the AGC amplifier is that the diodes are connected to the emitters of the differential transistor pair to improve the linearity. The maximum gain and 3-dB down bandwidth were 15 dB and 1.4 GHz, respectively, and a dynamic range of 25 dB was obtained. The preamplifier has a shunt-series feedback configuration. Furthermore, a gain and 3-dB down bandwidth of 22 dB and 2 GHz, respectively, were achieved with an optimum circuit design. The noise figure obtained was 3.5 dB.     

10Gb/s光接收机跨阻前置放大器芯片设计研究

采用0.18 μm BiCMOS工艺设计并实现了一种高增益、低噪声、宽带宽以及大输入动态范围的光接收机跨阻前置放大器.在寄生电容为250 fF的情况下,采用全集成的四级放大电路,合理实现了上述各项参数指标间的折中.测试结果表明:放大器单端跨阻增益为73 dB,-3 dB带宽为7.6 GHz,灵敏度低至-20.44 dBm,功耗为74 mW,最大差分输出电压为200 mV,最大输入饱和光电流峰-峰值为1 mA,等效输入噪声为17.1 pA/√Hz,芯片面积为800 μ.m×950μm.