A monolithic 2-b delta-sigma A/D converter

A monolithic 20-b analog-to-digital (A/D) converter using oversampling techniques which is implemented in standard 3-μm CMOS technology is described. The integrated circuit contains a fourth-order delta-sigma modulator and a digital finite-impulse-response filter and decimator. The modulator consists of a continuous-time chopper-stabilized front end, and a switched-capacitor loop filter and comparator. The dynamic range is 123 dB over a DC-to-500-Hz bandwidth, and the signal-to-noise-harmonic-distortion ratio is 126 dB. The chip consumes 125 mW power and has an area of 29.25 mm²     

A 1.2 V 12 b 60 MS/s CMOS Analog Front‐End for Image Signal Processing Applications

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front‐end (AFE) employing low‐power and flexible design techniques for image signal processing. An op‐amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog‐to‐digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 µm CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal‐to‐noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 mm² and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.     

A low-power stereo 16-bit CMOS D/A converter for digital audio

A low-power 16-bit CMOS D/A (digital/analog) converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is used. A geometric averaging technique is used to minimize the harmonic distortion of the converter at high signal levels. The dynamic range is 95 dB. The circuit operates in a time-multiplex mode at a sample frequency of 44 kHz in a power supply range of 2.5-5 V and has a power consumption of 15 mW. A 2-μm CMOS technology is used and the active chip area is 5 mm²      

Fully balanced CMOS current-mode circuits

A fully balanced current-mode circuit topology has been developed for analog signal processing applications. The basic building block, a 5-V fully balanced current mirror/amplifier, has been fabricated using a standard 2-μm n-well CMOS process. With a peak signal to bias current ratio i/I=0.5, the open-loop total harmonic distortion was-70 dB. With the addition of sampling switches, the current mirror/amplifier forms a fully balanced switched-current integrator that exhibits first-order cancellation of clock-feedthrough/charge-injection effects. Fully balanced SI ladder filters have been implemented using a 2-μm p-well CMOS process. For a sampling frequency of 128 kHz, the five-pole Chebyshev low-pass ladder filters met design specifications of 0.1-dB passband ripple and 5-kHz bandwidth. The dynamic range was 81.5 dB, and the total power dissipation was 14 mW with V_dd 5 V     

A 3-/spl mu/m CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting

A 3-/spl mu/m CMOS digital signal processor (DSP) performs speech signal shaping, programmable echo cancellation and gain setting functions for telephone applications. A/D and D/A conversions are performed by making use of /spl Sigma//Spl Delta/ modulators, decimator, and interpolator filter blocks. In addition, the DSP acts as a control interface between the subscriber line interface circuit (SLIC) and the line card controller, the denouncing of eight line status bits included.     

A 10 b 50 MHz pipelined CMOS A/D converter with S/H

A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology     

A total solution for a 9600-b/s modem transmitter chip

A single-chip analog transmitter (TX chip) for a V29-V32 9600-b/s modem has been implemented in a 3-μm CMOS n-well process. A high level of integration permits a low-cost, high-performance modem to be built. The TX chip is composed of analog, switched capacitor, and digital circuits. The important functions realized are the phase-point generator, the cosine roll-off low-pass filter, the modulator, and the programmable equalization filters. The chip occupies 29 mm² and dissipates 300 mW     

A CMOS oversampling D/A converter with a current-mode semidigitalreconstruction filter

Oversampling digital-to-analog (D/A) converters employing sigma-delta modulation noise shaping and single-bit quantization are attractive for use in digital audio applications because of their relaxed reconstruction filtering requirements and their tolerance of component mismatch. However, the use of a two-level D/A interface results in a large amount of out-of-band quantization noise that typically must be attenuated by a carefully designed analog reconstruction filter. This paper introduces a means of simplifying the reconstruction filter design through the use of a semidigital finite-impulse-response (FIR) filter. In particular, it describes an oversampling D/A converter wherein a current-mode semidigital reconstruction filter is used to implement a multilevel D/A interface that attenuates the out-of-band quantization noise without requiring precise component matching. An experimental implementation of the converter achieves a dynamic range of 94 dB and 72 dB attenuation of out-of-band quantization noise for a baseband of 20 kHz. The prototype converter, which consists of a linear interpolator, a second-order noise shaper, and a 128-tap semidigital FIR filter, dissipates 59 mW from a 5-V supply and occupies an active area of 3 mm² when integrated in a 1.2-μm digital CMOS technology     

A 125-MHz mixed-signal echo canceller for Gigabit Ethernet oncopper wire

A discrete-time analog echo canceller is described that reduces the echo in the front end of Gigabit Ethernet twisted-pair interfaces. Echo cancellation in the analog domain by means of four taps reduces the complexity of the digital echo canceller and crosstalk cancellers. Designed in a 0.4-μm CMOS technology, the circuit employs an LMS algorithm to adapt to the cable length and impedance discontinuities, providing an echo suppression of 10 dB. The design operates at 125 MHz while consuming 43 mW from a 3-V supply     

An analog front end for v.22bis modems

An analog front end for the 2400-b/s v.22bis modem has been implemented in a 3-μm CMOS process. A high level of integration in the front end results in a low-cost, high-performance modem system. A mix of analog switched-capacitor and digital circuits is used throughout the chip. Some of the major functional blocks are a modulator, tone generator, band-split filters, programmable receive gain stage, 8-bit ADC (analog-to-digital converters), bandgap voltage reference, and special signal detectors. Features are included to support a number of lower-speed, split-band modem standards. The chip occupies 59000 mils ² and dissipates 200 mW. System and circuit aspects of the design are discussed; measured performance of the IC and of the complete modem system are given     

A monolithic ΣΔ A/D and D/A converter with filter forbroad-band speech coding

The authors present a 5-V-only 14-b, 16 ksamples/s linear codec suitable as the audio part of a CCITT G722 codec. The device uses second-order sigma-delta modulation for both analog/digital (A/D) and digital/analog (D/A) conversion at 2.048 Msamples/s. A time-continuous modulator with integrated antialias filtering is used at the A/D side, obviating the need for an external antialiasing filter. The digital filters for decimation and interpolation are implemented with both a custom digital signal processor (DSP) and specialized hardware. The device was realized with 74000 transistors on a 31-mm² die in a 3-μm SACMOS technology. A dynamic range of more than 80 dB and a passband ripple of 0.3 dB were attained with A/D and D/A paths in cascade     

A BiCMOS analog front-end circuit for an FDM-based ADSL system

This BiCMOS analog front-end (AFE) integrated circuit contains the analog transmit function and a low-noise receiver for FDM-based ADSL systems. The IC includes a current steered 14-bit 5-Msps D/A converter, laser trimmed third-order reconstruction and anti-alias filters, a programmable attenuator with 200-ohm output drive capability, 60-dB of RX programmable gain, and a serial interface. Trimmable thin-film resistors allow ±4% filter cutoff frequency and absolute gain accuracy. The multitone power ratio performance of the part is approximately 65 dB with a spurious free dynamic range >70 dBc. The CMRR of the RX channel is >90 dB@1.1 MHz. PSRR for transmit and receive are greater than 60 dB. The isolation features of the 1.2-μm BiCMOS technology allow transmit and receive to operate in full-duplex mode with greater than 80 dB of cross-talk isolation. The chip size is 25.8 mm² which includes bond pads and electrostatic discharge protection devices     

A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system forAM/FM radio receivers

ΣΔ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time ΣΔ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm² in 0.25-μm standard digital CMOS. The ΣΔ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW     

A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signalbandwidth and 89 dB SNR

A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-μm CMOS process, cascades a second-order 5-b sigma-delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of -98 dB with a 100-kHz input signal     

A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells

A 31.3-dBm 900-MHz bulk CMOS T/R switch with transmit (TX) and receive (RX) insertion losses of 0.5 and 1.0 dB and isolation of 29 dB is demonstrated. The switch utilizes a floating-body technique, feed-forward capacitors, and 3-stack 3.3-V MOSFETs with 0.26-mum sub-design-rule (SDR) channel length. Using these, a 28-dBm 2.4-GHz T/R switch with TX and RX insertion losses of 0.8 and 1.2 dB, and isolation of 24 dB is also demonstrated. The power handling capability is limited by an abrupt output power drop before reaching the normal 1-dB compression point. The circuits are implemented in the UMC 130-nm mixed-mode triple-well CMOS process.     

A 20-Gb/s CMOS multichannel transmitter and receiver chip set forultra-high-resolution digital displays

A multichannel transmitter (TX) and receiver (RX) chip set operating at 20 Gb/s (5 Gb/s×4 ch) has been developed by using 0.25-μm CMOS technology. To achieve multichannel data transmission and high-speed operation, the chip set features: (1) circuits for compensating the phase difference between multiple RX chips, which is due to data skew resulting from different lengths of transmission cables, and for compensating the frequency difference between the system clocks of the TX and RX chips; (2) a self-alignment phase detector with parallel output for a high-speed data-recovery circuit; and (3) a fully pipelined 8B10B encoder. At a 2.5-V power supply, the power consumption of the TX chip during 5-Gb/s operation is 500 mW and that of the RX chip is 750 mW. Four of these TX/RX chip sets can provide an aggregate bandwidth of 20 Gb/s     

A single-chip universal digital satellite receiver with 480-MHz IFinput

This paper presents a complete single-chip universal digital satellite receiver supporting all current DBS system standards. The mixed-signal device accepts a modulated data stream at up to 90 Mbps and delivers a demodulated, error-corrected output data stream. The IC features an analog front end with 480-MHz intermediate frequency downconversion and dual 8-bit analog-to-digital converters, an all-digital BPSK/QPSK/OQPSK variable-rate receiver supporting 1-45 MBaud operation with phase/frequency recovery, variable-rate digital filters, square-root Nyquist matched filters, acquisition and tracking loops, and a DVB/DSS/DigiCipher I/II-compliant concatenated Viterbi/Reed-Solomon forward error correction decoder with on-chip deinterleaver RAM. All required clocks are generated on chip from a single reference crystal. The chip contains 1.2 million transistors in a die area of 22 mm² and was implemented in a single-poly 0.35-μm CMOS process with four layers of metal     

采用自适应信号处理技术的低成本回波抵消器

提出了一种低成本回波抵消电路方案,采用了自适应信号处理技术,可用于连续波雷达系统中的射频收发前端,能改善载波泄漏和收发隔离度指标,从而提高接收机前端的动态范围。仿真结果表明,在采用环形器作为收发隔离器件的典型应用条件下,采用回波抵消电路后,前端可以获得57 dB以上的收发隔离度改善。该电路结构简洁、算法运算量小、载波抑制特性稳定、收敛迅速,而且对器件指标的要求并不苛刻,有利于提高系统的经济性。     

A high-speed programmable CMOS interface system combining D/Aconversion and FIR filtering

This paper describes the design, integrated circuit realization, and experimental characterization of a high-speed programmable interface system combining the functions of digital-to-analog (D/A) conversion and FIR filtering. The system comprises four high-speed digital delay lines, with programmable delay length, together with four high-speed steering-current D/A converters with independent digitally-programmable gains. A demonstration prototype chip has been fabricated in a 1.2-μm digital CMOS technology. At 54 MHz conversion rate and digital delay lines clocked at 18 MHz, it consumes 115 mW for a full-scale output current of 13.3 mA at 5 V supply     

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design andperformance evaluation

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f_t were developed for the integrators. The circuit is implemented in a 1.75-μm 5-V CMOS process. The analog circuitry occupies 2 mm² of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software