CMOS ring oscillator with combined delay stages

Full transistor voltage control oscillators by delay stages are studied in this paper. First we describe the general conditions of oscillators and after introducing some common inverters, calculating their delay times, we analyze the dependence of delay time to variation of power supply voltage. The analyzing results show that the delay of basic type inverter varies in the opposite direction as that of current starved inverter, therefore to achieve better frequency stability versus voltage power supply changing, some combined structures of inverters are presented. The results of simulation by 0.18 CMOS technology library of HSPICE approve the analysis results.     

Temperature-compensated CMOS ring oscillator for power-management circuits

The design of a temperature-compensated CMOS ring oscillator is introduced. The concept is to make use of a linear, positively or negatively temperature-sloped supply voltage to power-up the ring oscillator. Experimental results show that the oscillation frequency remains fairly constant using the proposed scheme.     

Improved accuracy equation for propagation delay of a CMOS inverter in a single ended ring oscillator

In this paper the issue of obtaining an accurate equation for the delay of a CMOS inverter is explored. In the conventional equations provided for the propagation delay, many simplifying assumptions are made. Also some important events that occur during the charging/discharging of the capacitances are neglected. This reduces the accuracy of the conventional delay equations. Since the propagation delay time is used in many applications, such as obtaining the ring oscillator frequency, its accuracy is very important. Hence, we calculate an accurate equation for the propagation delay time. The intricacies and challenges in deriving an improved accuracy equation will be addressed. The approach of deriving an improved equation is explained in detail. The accuracy of the derived equation is verified through simulation. We will look into the obtained equation to evaluate the effect of different parameters on the delay and compare the improved and conventional equations.     

Oscillation-controlled CMOS ring oscillator for wireless sensor systems

This paper presents a ring oscillator with the function of the oscillation controlled for wireless sensor systems (WSSs). The proposed oscillator consists of a NAND gate, 4 inverters, and 1-, 3-, 9-times buffer stage. Operation of it is controlled by the NAND gate. The oscillator can reduce the power loss because the oscillator is oscillated during only high level input. The proposed oscillator was designed and fabricated by 2.5 μm CMOS technology, through which it is possible to realize a WSS on a single chip because a sensor and an oscillator can be fabricated concurrently.The frequency tuning range of the oscillator was found to be approximately 90–152 MHz and the output power of the oscillator was ?8.42 dBm. The measured phase noise is ?99.35 and ?102.59 dBc/Hz at 1 and 5 MHz offsets, respectively, from the carrier of 152 MHz. Power consumption of the oscillator is determined by the duty cycle of the input signal pulse, and the range of power consumption was measured as 1.5–45 mW at the duty cycle of 1.0.     

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80 nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016 mm² with under 1 μW power consumption for providing 0.7 °C effective resolution at 1 sample/s processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.     

A low-phase-noise 900-MHz CMOS ring oscillator with quadrature output

A 900-MHz two-stage CMOS voltage controlled ring oscillator (VCRO) with quadrature output is presented. The circuit is designed in a 0.18-um CMOS technology and operated on a 1.8-V supply voltage. The VCRO have a tuning range of 730 MHz to 1.43 GHz and good tuning linearity. Between 0 V and 1.1 V of control voltage, the gain of VCRO is around −620 MHz/V. At 900 MHz, the phase noise of the VCRO is −106.1 dBc/Hz at 600-KHz frequency offset with power consumption of 65.5 mW.     

Temperature compensated and gated CMOS ring oscillator for time-to-digital converter application

This paper presents a CMOS voltage controlled ring oscillator with temperature compensation for low power time-to-digital converters (TDCs). In order to maintain the oscillation frequency stable, a novel compensation circuit is proposed through adaptively sensing temperature variations. This design has been implemented in TSMC 0.35 μm CMOS standard process with an active area of under 0.039 mm². Experimental results show that the clock frequency is around 159.0 MHz only with a power consumption of 550 μA. As respective to the room temperature the maximum frequency variation is between ?3.46 and +3.08 % under temperature range of ?40 to 85 °C. The bit error time induced by clock jitter is limited within 4.8 % in the whole clock period, and the differential nonlinearity of the TDC is less than 0.408 LSB.     

Versatile multi-decade CMOS voltage-controlled oscillator with accurate amplitude and pulse width control

A compact, versatile and very high speed approach for waveform generation is introduced. It generates triangle and square waveforms. The VCO has a very wide range of oscillating frequencies, from fractions of Hz to 30 MHz in 0.5 μm CMOS technology. The amplitude of the oscillations can be very precisely controlled. It has linear control over frequency, amplitude and pulse-width. It can be used in frequency, amplitude and pulse-width modulation applications as well as in the accurate piecewise linear waveform synthesis. Experimental results of a MOSIS CMOS AMI 0.5 μm technology test chip are presented that validate the proposed circuit.     

Frequency equation for the submicron CMOS ring oscillator using the first order characterization

By utilizing the first order behavior of the device,an equation for the frequency of operation of the submicron CMOS ring oscillator is presented.A 5-stage ring oscillator is utilized as the initial design,with different Beta ratios,for the computation of the operating frequency.Later on,the circuit simulation is performed from 5-stage till 23-stage,with the range of oscillating frequency being 3.0817 and 0.6705 GHz respectively.It is noted that the output frequency is inversely proportional to the square of the device length,and when the value of Beta ratio is used as 2.3,a difference of 3.64％ is observed on an average,in between the computed and the simulated values of frequency.As an outcome,the derived equation can be utilized,with the inclusion of an empirical constant in general,for arriving at the ring oscillator circuit's output frequency.     

粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

Full range voltage-controlled ring oscillator in 0.18μm CMOS for low-voltage operation

A new differential delay cell with a complementary current control to increase the control voltage range as well as the operation frequency is proposed for low-voltage operation. The new differential delay cell is employed in a four-stage voltage-controlled ring oscillator (VCRO). The VCRO is implemented using 0.18 m 1P6M CMOS process and 1.8 V supply voltage. Measured results show that a wide operation frequency range from 5.36 to 3.03 GHz is achieved for the full range control voltage from 0 to 1.8 V. Measured phase noise is 107 dBc/Hz at 1 MHz offset from the 5.22 GHz centre frequency.     

Design and frequency/phase-noise analysis of a 10-GHz CMOS ring oscillator with coarse and fine frequency tuning

A 10-GHz CMOS ring oscillator that employs a multi-pass technique for boosting its frequency is proposed in this paper. The proposed circuit allows the tuning gain to be lowered by deploying the coarse/fine frequency tuning whilst maintaining wide frequency coverage. The small signal model of the proposed delay stage and the circuit operation are discussed in this paper. The time-variant analysis presented permits accurate prediction of the frequency tuning characteristic and the results have been verified by simulation. The phase noise analysis is also discussed in detail to provide better insight to the noise that is contributed by each transistor. The calculated results agreed well with that of the simulations. Hai Qi Liu was born in Jiangsu, China, in 1979. He received the B.S. and M.Sc. degrees, both in electrical engineering from the Tianjin University, Tianjin, China, in 2000, and Tongji University, Shanghai, China, in 2003, respectively. He is currently working toward the Ph.D. degree at the Nanyang Technological University, Singapore. His research focuses mainly on the design of fully integrated oscillators and Phase-Locked Loops for optical communication applications. His research interests also include RF frequency synthesizers and RF front-end designs for wireless applications. Wang Ling Goh obtained both her B.Eng and Ph.D. degrees from the department of Electrical and Electronic Engineering at the Queen’s University of Belfast (QUB) in United Kingdom. When working on her Ph.D., she was also engaged as a research associate at the Northern Ireland Semiconductor Research Centre (NISRC) at QUB. Dr Goh joined the School of Electrical and Electronic Engineering at the Nanyang Technological University (NTU) in Singapore as a lecturer in January 1996. She is now an Associate Professor in the Division of Circuits and Systems, School of Electrical & Electronic Engineering. Dr Goh has to-date co-authored 1 book, filed 13 patents (granted), and published about 60 research papers in international conferences and journals. Her research interests are in areas of silicon device processing technologies as well as digital and mixed-signal IC designs. Liter Siek received the B.A.Sc. degree from University of Ottawa, Ontario, Canada; the M.Eng.Sc. from University of New South Wales, Sydney, Australia; and the Ph.D. from Nanyang Technological University, Singapore. From 1981 to 1983 he was employed in several companies in the area of automation and control. From 1983 to 1985, he was with SGS, currently known as ST Microelectronics situated in Castelletto, Milan, Italy, where he worked in the central R&D Laboratories for Linear IC. From 1985 to 1987, he was with the same company situated in Singapore’s Asia Pacific Design Center. Since October 1988, he has been with Nanyang Technological University. His research interests are in the design of bipolar, CMOS and BiCMOS analog/mixed signal ICs. In addition, he has authored and co-authored 53 international journal/conference technical papers.     

A mixed-signal 0.18-μm CMOS SoC for DVD systems with432-MSample/s PRML read channel and 16-Mb embedded DRAM

This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD RAM and ROM systems. It integrates a 32-b RISC CPU, formatter, servo digital signal processor (DSP), 16-Mb DRAM, error correction code (ECC), ATA interface, and partial-response-maximum-likelihood (PRML) read channel with 7-b interpolated parallel analog-to-digital converter (ADC). Increasing the bus bandwidth by using embedded DRAM, a hardware ECC engine, and four parallel digital finite-impulse response (FIR) filters contributes to the high playback speed of 16×. PR(3,4,4,3) architecture has been used in the read channel system for optical disc systems. The obtained wide tangential tilt margin of ±0.6° is due to the use of this PRML read channel technique. The interpolated parallel scheme has attained a high number of effective bits of 6.3 for 72-Mz input frequency at 432-MSample/s operation without any calibration technique, with low power consumption of 180 mW in a small core size of 1.05 mm². This SoC has been fabricated in 0.18-μm 1PS3AL CMOS embedded DRAM technology. It contains 24 million transistors in a 144-mm ² die and consumes 1.2 W at 432-MSample/s operation. This low power consumption allows the use of a low-cost plastic package. As a result, we can compose highly reliable DVD RAM and ROM systems with this SoC and some tiny components     

A CMOS multichannel IC for pulse timing measurements with 1-mVsensitivity

A multichannel data acquisition circuit that measures the occurrence times of input pulses relative to a 62.5-MHz clock has been integrated in a 1.2-μm CMOS technology. The pulse timing measurement channels are sensitive to input pulses with peak amplitudes as small as 1 mV. Each channel consists of a wideband preamplifier, a tail-cancellation filter, a timing discriminator with time-walk compensation, and a time digitizer. A phase-locked loop (PLL) reference for the time digitizer is included in the circuit. An overall channel timing error of 0.46 ns RMS has been achieved, with negligible channel-to-channel crosstalk, at a power dissipation of 50 mW/channel     

一款宽供电电压范围工作的植入式神经信号记录前端芯片

摘要：本文设计了一款宽电压供电范围、用于神经电信号采集的前端芯片。该芯片主要由前端放大电路、仪表放大器（IA）和循环结构模数转换器（CADC）构成。在不采用分立元件的情况下,前端放大电路采用电容耦合、电容反馈的拓扑结构,结合伪电阻的应用,产生一个小于1Hz的-3dB高通频率截止点。双运算仪表放大器用于进一步提高增益的同时也为后续的模数转换电路提供一个较低的输出阻抗。前端放大电路和仪表放大电路共提供45.8dB的增益,其等效输入参考噪声电压为6.7uV从1Hz~5KHz积分）。放大后的信号被12位采样精度的ADC采样,该ADC最高采样速率为139KS/s,有效位数为8.7位。整个电路在1.34V到3.3V供电范围内消耗的总电流为165uA到 216uA。该芯片采用联华电子公司（UMC）的0.18-um 工艺制造,总面积1.06mm2 。该芯片在仿真生理环境下成功地记录到了神经电信号。     

A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node

In this letter, we have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (W/sub fin/ = 10 nm) and tall (H/sub fin/ = 60 - 80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain-induced barrier leakage characteristics of 45 mV/V at V/sub dd/ = 1 V and L/sub g/ = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the V/sub T/ at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (W/sub fin/ = 65 nm) with I/sub dsat/ = 380 /spl mu/A//spl mu/m at I/sub off/ = 60 nA//spl mu/m and V/sub dd/ = -1.2 V.     

A phase-noise reduction technique for RF CMOS voltage-controlled oscillator with a series LC resonator

This paper proposes a novel phase-noise reduction technique for high performance voltage-controlled oscillator (VCO) using a cross-coupled series LC resonator, rather than parallel LC resonator. The proposed technique makes a time difference between the zero crossing point of the drain node voltages and that of the gate node voltages of the switching pair. By adding cross coupled PMOS loading, the drain voltages are made close to a rectangular shape, which makes an ideal on–off switching of the VCO. Since the current source contributes large portion of noise to the output, it is removed in the proposed VCO to further improve the noise performance. While the series connected inductor and capacitor enhances the fundamental frequency swing at the LC connection node, it gives a cleaner spectral purity output and suppresses the overall noise at the drain node of the cross-coupled switching cell.     

一种应用于无线局域网具有3.01-3.82 GHz频率范围和6.29%调谐增益变化的CMOS LC压控振荡器

A wideband low-phase-noise LC voltage-controlled oscillator （VCO） with low VCO gain （Kvco） vari- ation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low Kvco variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured Kvco is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of-121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.     

A ring oscillator with very low phase noise and wide frequency range using carbon nanotube technology for PLL applications

This paper presents a wide frequency range three-stage voltage-controlled ring oscillator in CNTFET technology. The advantages of CNTFETs are the high speed of charge carriers, high signal to noise ratio, small size and ballistic transport. Therefore in comparison with MOSFETs, they have a higher frequency, and can operate at a wide frequency range with a very low phase noise if forward bulk bias and active inductor techniques are simultaneously used in the oscillators that employ CNTFETs. In this paper, the Stanford CNTFET model is implemented in Verilog-A, and the proposed CNT ring oscillator is simulated using ADS software over the 50–500 GHz frequency range. The phase noise of the oscillator is ? 136 dBc/Hz at 1 MHz offset, which is suitable for PLL applications.