超薄芯片叠层封装器件热可靠性分析

采用通用有限元软件MSC.Marc,模拟分析了一种典型的多层超薄芯片叠层封装器件在经历回流焊载荷后的热应力及翘曲分布情况,研究了部分零件厚度变化对器件中叠层超薄芯片翘曲、热应力的影响。结果表明:在整个封装体中,热应力最大值(116.2 MPa)出现在最底层无源超薄芯片上,结构翘曲最大值(0.028 26 mm)发生于模塑封上部边角处。适当增大模塑封或底层无源芯片的厚度或减小底充胶的厚度可以减小叠层超薄芯片组的翘曲值;适当增大底层无源超薄芯片的厚度(例如0.01 mm),可以明显减小其本身的应力值10 MPa以上。     

2048×2048 HgCdTe红外焦平面杜瓦冷头热应力有限元分析

利用有限元方法对2048×2048(15 μm)红外焦平面杜瓦冷头的原始结构以及加入的平衡层结构进行了分析.在陶瓷基板下方增加膨胀系数较小的平衡层,对探测器芯片变形及热应力有一定的缓解作用.通过增大AlN平衡层上表面的直径,减小了芯片中心以外的翘曲范围,缓解了应力过于集中的问题.当直径超过芯片对角长度时,最大热应力骤减,最终趋于稳定;芯片变形量随之迅速减小.在直径为36 mm时,达到最小值(6.86 μm);随后缓慢增加并趋于稳定.当AlN平衡层的直径超过芯片对角长度后,AlN平衡层的厚度对芯片变形的影响开始减小.通过加入AlN平衡层能够有效改善大面阵焦平面探测器芯片的变形及热应力,同时通过调节AlN平衡层的结构,可进一步优化探测器杜瓦组件的可靠性.     

基于析因实验设计的QFN热可靠性分析

在微电子封装器件的生产或使用过程中,由于封装材料热膨胀系数不匹配,不同材料的交界处会产生热应力,热应力是导致微电子封装器件失效的主要原因之一。文章采用MSC．Marc有限元软件,分析了QFN器件在回流焊过程中的热应力、翘曲变形、主应力及剪应力,并由析因实验设计得到影响热应力的关键因素。研究表明：在回流焊过程中,QFN器件的最大热应力出现在芯片与粘结剂接触面的边角处;主应力和剪切应力的最大值也出现在芯片与粘结剂连接的角点处,其值分别为21．42MPa和-28．47MPa;由析因实验设计可知粘结剂厚度对QFN热应力的影响最大。     

WLCSP中微焊球结构尺寸对其热应力的影响

晶圆级芯片尺寸封装(WLCSP)微焊球结构尺寸对其热机械可靠性有重要的影响。通过二维有限元模拟筛选出对WLCSP微焊球及其凸点下金属层(UBM)中热应力影响显著的参数,采用完全因子实验和多因子方差统计分析定量评估各种因子影响的显著性,最后建立三维模型,用子模型技术研究关键尺寸因子对热应力变化的影响。研究发现,焊球半径是影响焊球热应力的最关键尺寸因子,电镀铜开口和铜焊盘厚度对焊球热应力的影响也较显著;钝化层开口和焊球半径是影响UBM热应力的最关键尺寸因子。随着焊球半径增大,焊球热应力减小。     

基于析因实验设计的QFN热可靠性分析

在微电子封装器件的生产或使用过程中,由于封装材料热膨胀系数不匹配,不同材料的交界处会产生热应力．热应力是导致微电子封装器件失效的主要原因之一。采用MSC．Marc有限元软件．分析了QFN器件在回流焊过程中的热应力、翘曲变形、主应力及剪应力,并由析因实验设计得到影响热应力的关键因素。研究表明：在回流焊过程中,QFN器件的最大热应力出现在芯片与粘结剂接触面的边角处：主应力和剪切应力的最大值也出现在芯片与粘结剂连接的角点处．其值分别为21．42MPa和-28．47MPa：由析N实验设计可知粘结剂厚度对QFN热应力的影响最大。     

基于析因实验设计的QFN热可靠性分析

在微电子封装器件的生产或使用过程中,由于封装材料热膨胀系数不匹配,不同材料的交界处会产生热应力,热应力是导致微电子封装器件失效的主要原因之一。本文采用MSC．Marc有限元软件,分析了QFNN件在回流焊过程中的热应力、翘曲变形、主应力及剪应力,并由析因实验哼殳计得到影响热应力的关键因素。研究表明：在回流焊过程中,QFN器件的最大热应力出现在芯片与粘结剂接触面的边角处;主应力和剪切应力的最大值也出现在芯片与粘结剂连接的角点处,其值分别为21．42MPa和-28．47MPa;由析因实验设计可知粘结剂厚度对QFN热应力的影响最大。     

PCBA结构参数与振动谱型对BGA焊点疲劳寿命的影响

为获得印制电路板组件(PCBA)的板厚、芯片布局等结构参数和随机振动谱型(功率谱密度,PSD)变化对球栅阵列(BGA)封装芯片焊点振动疲劳寿命的影响,利用HYPERMESH软件建立了带BGA封装芯片的PCBA三维有限元网格模型,并采用ANSYS软件对PCBA有限元模型进行了随机振动响应分析。结果表明,随着PCB厚度增加,BGA焊点振动疲劳寿命呈现明显提升的趋势,当PCB厚度由1.2 mm增加到2.2 mm时,BGA焊点振动疲劳寿命N由45363大幅增加到557386;合理的芯片安装间距能够明显增加焊点振动疲劳寿命,特别是当芯片安装在靠近固定约束并处于两个约束对称中间位置时;当PCBA的第一阶固有频率位于随机振动谱最大幅值对应的频率区间时,BGA焊点的振动疲劳寿命会明显降低。     

塑封器件回流焊与分层的研究

由于无铅焊料的应用,回流焊的温度提高影响了塑封器件的质量和可靠性。针对实际的LQFP器件,利用有限元软件建立三维模型,分析了塑封器件在潮湿环境中的湿气扩散及回流焊中的形变和热应力分布,并讨论了塑封料参数及细小裂纹对分层的影响。结果表明,在湿热的加载下,塑封器件的顶角易发生翘曲现象;芯片与塑封料界面处易分层,导致器件失效。     

PBGA固化后产生翘曲的有限元模拟分析

由于PBGA器件中各材料热膨胀系数有差异,固化后易产生翘曲变形。采用有限元模拟法对PBGA器件的EMC封装固化和后固化过程进行了分析。结果表明:固化过程是影响翘曲的关键过程,残余应力增加,翘曲变形有所增加。如固化后最大残余应力为95.24MPa,翘曲位移为0.1562mm;后固化以后最大残余应力为110.3MPa,翘曲位移为0.1674mm,翘曲位移增加值仅为0.0112mm。适当增加硅粉填充剂的含量,可以减小固化工艺后的翘曲变形。     

灰色关联分析选区激光烧结成型研究

选区激光烧结(SLS)是重要的3D技术之一。烧结高分子材料成型过程中,材料的不均匀收缩导致制件翘曲变形及尺寸减小。而在烧结过程中工艺参数起着主要影响作用。激光烧结聚丙烯(PP)复合粉末成型过程中,采用各工艺参数不同水平组合烧结成型制件;用灰色关联分析法(GRA)研究工艺参数对成型精度的影响。结果表明,对于翘曲量及尺寸精度最重要的影响因子为扫描速度。综合工艺参数对翘曲量和尺寸误差的影响,得到激光烧结PP制件的优化工艺参数:扫描速度为1.9 m/s,激光功率为16.5 W,铺粉厚度为0.15 mm,扫描间距为0.12 mm。     

Effects of build-up printed circuit board thickness on the solderjoint reliability of a wafer level chip scale package (WLCSP)

The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvias. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the PCB with microvia build-up layer become much more significant than that without the microvia build-up layer     

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.     

Solder joint crack propagation analysis of wafer-level chip scalepackage on printed circuit board assemblies

The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mechanics with finite element method. Furthermore, an empirical equation for predicting the thermal-fatigue life of flip chip solder joints is proposed     

Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints ofwafer level chip scale package on buildup microvia printed circuit board

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies     

Sensitivity Design of DL-WLCSP Using DOE With Factorial Analysis Technology

Newer, faster, and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm² without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEMs). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing     

Critical issues of wafer level chip scale package (WLCSP) withemphasis on cost analysis and solder joint reliability

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study     

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design     

Estimation of warpage and thermal stress of IVHs in flip–chip ball grid arrays package by FEM

Flip–chip substrates have been developed to meet the recent technical trend. They have a small IVH (Inner Via Hole) diameter to improve electrical packaging performance. However, under thermal loading conditions, substrate warpage increases as substrate thickness decreases. Performance of FCBGA may be severely limited by substrate warpage. Furthermore, large thermal deformation induces cracks and delaminations in an IVH. It is important to understand substrate thermal deformation to improve FCBGA reliability.Thermal deformation of the FCBGA (Flip–Chip Ball Grid Array) with assembly conditions has been calculated globally by finite element analysis. And residual plastic strain of an IVH has been estimated microscopically to understand thermal stress of the IVH. Finite element method considering non-linear material model is verified with experiment on warpage to improve simulation accuracy. Also, the Taguchi method is applied to optimize FCBGA substrate design.Based on the computed results by the Taguchi method, we know core thickness in FCBGA substrate is the most determining factor for thermal deformation. The second most significant factor is the core material properties. Even though the plugging material in the IVH has little thermal deformation macroscopically with respect to the entire FCBGA substrate, the plugging material lowers the reliability of the IVH alone microscopically. In some cases depending on the plugging material, the IVH may develop some cracks.