压控振荡器研制过程中的问题探讨

本文深入地讨论了VCO调试过程中出现的停振、跳模、功率小、线性差等现象,提出了展宽电调频率范围的若干措施.按照这些分析进行调整的VCO具有较高的技术指标.     

X波段宽带低相噪压控振荡器

简述了X波段宽带压控振荡器的压控灵敏度线性问题和降低其输出相噪的方法,同时给出了有关分析和实验结果.     

一种宽带低相噪CMOS LC压控振荡器设计

设计了一种频率可调范围约830MHz全集成CMOS LC压控振荡器.该压控振荡器利用了一种改进的四位二进制加权的开关电容阵列扩大了其调谐范围;采用了可变尾电流源设计,使得振荡信号在整个频率范围内幅度变化不大.结果表明,该压控振荡器总调节范围1.12～1.95GHz,功耗为6.5～19.1mW,采用0.35μm CMOS RF工艺设计版图面积为360μm×830μm,工作于1.1GHz和1.9GHz时,1MHz频偏处的单边带相位噪声分别为-122dBc/ Hz、-120dBc/ Hz.     

W波段InP DHBT宽带高功率压控振荡器（英文）

成功实现了一款具有高输出功率和宽频率调谐范围的基波压控振荡器.其制作工艺为0. 8μm InP DH-BT工艺,晶体管的最大fT和fmax分别为170和250 GHz.电路核心部分采用了为高频应用改进的平衡式考毕兹拓扑,在后面添加一级缓冲放大器来抑制负载牵引效应,并提升了输出功率. DHBT的反偏CB结作为变容二极管来实现频率调谐.芯片测试结果表明,压控振荡器的频率调谐范围为81～97. 3 GHz,相对带宽为18. 3%.在调谐频率范围内最大输出功率为10. 2 dBm,输出功率起伏在3. 5 dB以内.在该压控振荡器的最大调谐频率97. 3 GHz处相位噪声为-88 dBc/Hz@1MHz.     

X波段宽带压控振荡器的研制

本文论述了宽带压控振荡器的主要技术指标,基本原理及结构设计,性能及其分析。该振荡器具有低噪声、高稳定度、电调带宽宽等优点。     

宽频率范围的单子带压控振荡器设计

基于TSMC 180 nm CMOS工艺,提出了一种振荡频率为2～3 GHz的宽频率范围、低相位噪声的单子带压控振荡器(VCO).采用双平衡吉尔伯特混频结构,将单子带5～6 GHz压控振荡器与固定频率3 GHz压控振荡器进行下混频,可得到振荡频率为2～3 GHz的单子带压控振荡器,实现相对带宽从18.18％到40％的展...     

一种面向IEEE 802.11ac标准的5 GHz LC压控振荡器

基于TSMC RF 0.18 μm CMOS工艺,设计了一种可应用于IEEE 802.11ac标准的5 GHz宽带LC压控振荡器。该振荡器采用了NMOS交叉耦合结构,同时采用了5位开关电容阵列以扩展调谐范围。开关电容阵列使压控振荡器的增益KVCO保持在一个较小的值,有效地降低了压控振荡器的相位噪声。后仿真结果表明,该压控振荡器在1.8 V电源电压下,功耗为9 mW,频率调谐范围为4.52~5.56 GHz,在偏离中心频率1 MHz处仿真得到的相位噪声为-124 dBc/Hz。该LC 压控振荡器的版图尺寸为320 μm×466 μm。     

高频宽调节范围压控振荡器设计研究

设计了一种基于0.18μm CMOS工艺模型的超高频宽调节范围的压控振荡器.系统采用3级环形压控振荡器结构,每级采用调节尾电流的方式,实现了2.5 GHz至5 GHz以上的高频宽调节范围.系统在输出频率为5 GHz时,在5 MHz频偏处的相位噪声为-89.26 dBc/Hz.此次设计的压控振荡器可广泛应用于各种嵌入式系统或ADC中,为其提供在大范围内可调节的时钟.     

切换式调谐CMOS 压控振荡器

在现有的CMOS RF工艺条件下。利用“切换式调谐”设计思想完成了宽带调谐的压控振荡器(vco)的电路设计和版图设计。用Candence SpectreRF软件进行了模拟。结果表明。该VCO在保证其它性能指标的同时，实现了宽的频率覆盖。     

60GHz宽调谐范围推—推压控振荡器设计

基于65nmCMOS工艺实现了60GHz推—推压控振荡器（VCO）设计。采用互补交叉耦合去尾电流源结构以降低相位噪声。压控振荡器输出包含两级缓冲放大器,第二级缓冲放大器偏置在截止区附近以增大二次谐波的输出功率。在1.2/0.8V电源电压下,压控振荡器核心和缓冲放大器分别消耗2.43mW和2.95mW。在偏离中心频率1MHz处相位噪声为-90.7dBc/Hz。输出功率为-2.92dBm。特别的,压控振荡器的调谐范围达到9.2GHz（15.3%）,与调谐范围相关的性能指标FOMT为-182.7dBc/Hz。该压控振荡器可应用于57GHz～64GHz开放频段超高速短距离无线通信。     

基于石英基片的W波段高输出功率肖特基二极管倍频器

W-band quartz based high output power fix-tuned doublers are analyzed and designed with planar Schot- tky diodes. Full-wave analysis is carried out to find diode embedding impedances with a lumped port to model the nonlinear junction. Passive networks of the circuit, such as the low pass filter, the E-plane waveguide to strip transitions, input and output matching networks, and passive diode parts are analyzed by using electromagnetic simulators, and the different parts are then combined and optimized together. The exported S-parameters of the doubler circuit are used for multiply efficiency analysis. The highest measured output power is 29.5 mW at 80 GHz and higher than 15 mW in 76-94 GHz. The highest measured efficiency is 11.5% at 92.5 GHz, and the typical value is 6.0% in 70-100 GHz.     

Wide tuning-range CMOS VCO based on a tunable active inductor

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.     

功率为16.9 dBm增益大于20 dB的InP DHBT W波段功率放大器

A two-stage MMIC power amplifier has been realized by use of a l-μm InP double heterojunction bipolar transistor(DHBT).The cascode structure,low-loss matching networks,and low-parasite cell units enhance the power gain.The optimum load impedance is determined from load-pull simulation.A coplanar waveguide transmission line is adopted for its ease of fabrication.The chip size is 1.5×1.7 mm~2 with the emitter area of 16×1μm×15μm in the output stage.Measurements show that small signal gain is more than 20 dB over 75.5-84.5 GHz and the saturated power is 16.9 dBm @ 79 GHz with gain of 15.2 dB.The high power gain makes it very suitable for medium power amplification.     

一种面向多标准无线收发器的低功耗宽调谐范围基带滤波器设计

本论文提出了一种面向多标准收发器的具有精确片上调谐电路的低功耗宽调谐范围基带滤波器。设计的滤波器是由三级Active-Gm-RC类型的双二次单元级联组成的六阶巴特沃斯低通滤波器。采用改进的线性化技术来提高低通滤波器的线性度。论文提出了一种新的匹配性能与工艺无关的跨导匹配电路和具有频率补偿的频率调谐电路来增加滤波器的频率响应精度。为了验证设计方法的有效性,采用标准的130nm CMOS工艺对滤波器电路进行流片。测试结果表明设计的低通滤波器带宽调谐范围为0.1MHz-25MHz,频率调谐误差小于2.68%。滤波器在1.2V的电源电压下,功耗为0.52mA到5.25mA,同时取得26.3dBm的带内输入三阶交调点。     

A coupled-inductor dual-mode switched voltage-controlled oscillator using GaN-on-Si HEMT technology

A coupled-inductors dual-mode switch cross-coupled pair voltage-controlled oscillator (VCO) was presented, adopting GaN-on-Si high-electron-mobility transistor technology. The coupled inductors create two resonant frequencies that cover a wide frequency range. The two continuous bands were achieved by using coupled inductors, and the fine-tuning is controlled by varactors. The low and high bands of the VCO were 2.77–3.11 GHz and 3–3.28 GHz, in the V_c range between 10 and 17 V, respectively, which corresponds to a 16.7% (510 MHz) tuning range. The lowest phase noise was ?123 dBc/Hz at an offset frequency of 1 MHz, and the highest output power was 17.7 dBm using a 7.5-V power supply.     

Design of a three-stage ring-type voltage-controlled oscillator with a wide tuning range by controlling the current level in an embedded delay cell

This paper presents a new design for a three-stage voltage-controlled differential ring oscillator embedded with a delay cell for a wide tuning range from 59 MHz to 2.96 GHz by adjusting the current level in the delay cell. The ring oscillator consists of a voltage-to-current converter, coder circuit, three-stage ring with delay cells, and current monitoring circuit to extend the tuning range of the proposed voltage-controlled oscillator. Each functional block has been designed for a minimum power consumption using the TSMC 0.18 μm CMOS technology. We simulate the performances of the proposed voltage-controlled oscillator in terms of phase noise, power consumption, tuning range, and gain. Our simulation results show that the proposed oscillator has the linear frequency–voltage characteristics over a wide tuning range. At each tuning range (mode), the calculated phase noise of the proposed ring oscillator at each tuning range (mode) was −87, −85, −81, and −79 dBc/Hz at a 1 MHz offset from the center frequency. The DC power of the proposed voltage-controlled oscillator consumed 0.86–3 mW under a 1.8 V supply voltage.     

基频光退偏对大动态范围高效三倍频效率的影响

选择了ICF物理实验中适合于整形脉冲高效三倍频的Ⅰ/Ⅱ角度失谐和Ⅱ/Ⅱ偏振失配双倍频双混频方案,考虑了入射基频光退偏效应的影响,对倍频效率进行详细地数值模拟计算和对比分析,所得结果对工程设计具有参考价值.     

一种光接收机中的高增益宽动态范围跨阻放大器

As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range （DR） to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.