Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates

An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency. If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley & Sons, Ltd.     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.     

Power‐delay optimization of D‐latch/MUX source coupled logic gates

In this paper a design strategy for MUX, XOR and D‐latch source coupled logic (SCL) gates is proposed. To this end, an analytical model of the delay and the noise margin as a function of the transistors' aspect ratio and bias current is first introduced. Successively, analytical equations of the transistors' aspect ratio to meet a given noise margin specification are derived as a function of the bias current, and are then used along with the delay model to express the delay as an explicit function of the bias current and noise margin. The simplified delay expression explicitly relates speed performance to power dissipation and the noise margin, thereby providing the designer with the required understanding of the trade‐offs involved in the design. Therefore, the criteria proposed allow the designer to consciously manage the power‐delay trade‐off. The delay dependence on the logic swing is also investigated with results showing that this delay is not necessarily reduced by reducing the logic swing, in contrast with the usual assumption. Since the results obtained are valid for all SCL gates and are independent of the CMOS process used, the guidelines provided afford a deeper understanding of SCL gates from a design point of view. Copyright © 2005 John Wiley & Sons, Ltd.     

Analyzing noise robustness of wide fan‐in dynamic logic gates under process variations

Wide fan‐in dynamic logic gates are difficult to design due to the large number of leaky evaluation paths connected to the dynamic node. Designers have to cope with their low noise tolerance further worsened by the effects of process parameter variation. In this paper, a novel analytical model is derived and validated to evaluate the noise robustness of wide fan‐in dynamic logic gates taking process variation effects into account. Experiments were performed using a commercial 45‐nm 1‐V CMOS technology, and the noise robustness in terms of unity noise gain (UNG) was evaluated for 16 and 32‐bit OR gates. Obtained results demonstrate that the proposed model is able to predict the mean value of the UNG with a maximum error of only 6.8%, whereas the difference between the predicted and simulated UNG yield is always lower than five percentage points. Copyright © 2012 John Wiley & Sons, Ltd.     

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

This paper presents an automatic method for sizing the transistors in CMOS gates. The method utilizes a feedback control system to efficiently optimize the transistor sizes in small and large fan‐in gates, with the primary goal of enhancing noise robustness (as characterized by the static noise margin). The gates retain their robustness under threshold‐voltage variations over a range of supply voltages. The optimized gates not only expend reduced power and energy, but also take up less area than the conventional ones. These multi‐faceted gains, however, do incur some performance loss. Copyright © 2014 John Wiley & Sons, Ltd.     

Asynchronous sum‐of‐products logic minimization and orthogonalization

We propose a method of the asynchronous sum‐of‐products (SOP) logic simplification that comprises of minimization and orthogonalization. The method is based on a transformation of the conventional single‐rail SOP synchronous logic into the dual‐rail asynchronous one operating under so‐called modified weak constraints. We formulate and prove the product terms constraint that ensures a correct logic behavior. We have processed the MCNC benchmarks and generated the asynchronous SOP logic. The complexity of the logic obtained is compared with the state‐of‐the‐art representation. Using our approach, we achieve a significant improvement. Copyright © 2012 John Wiley & Sons, Ltd.     

Analytical estimation of propagation delay and short‐circuit power dissipation in CMOS gates

An efficient analytical method for calculating the propagation delay and the short‐circuit power dissipation of CMOS gates is introduced in this paper. Key factors that determine the operation of a gate, such as the different modes of operation of serially connected transistors, the starting point of conduction, the parasitic behaviour of the short‐circuiting block of a gate and the behaviour of parallel transistor structures are analysed and properly modelled. The analysis is performed taking into account second‐order effects of short‐channel devices and for non‐zero transition time inputs. Analytical expressions for the output waveform, the propagation delay and the short‐circuit power dissipation are obtained by solving the differential equations that govern the operation of the gate. The calculated results are in excellent agreement with SPICE simulations. Copyright © 1999 John Wiley & Sons, Ltd.     

电流型Z源逆变器的三值逻辑空间矢量控制策略

分析了实现电流型Z源逆变器三值逻辑空间矢量控制的原理,给出了基于Matlab Simulink的仿真模型及其实现方法.仿真结果验证了该控制策略的合理性和可行性.     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

In this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley & Sons, Ltd.     

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

The continued downscaling of CMOS technology has resulted in very high performance devices, but power dissipation is a limiting factor on this way. Power and performance of a device are dependent on process, temperature, and workload variation that makes it impossible to find a single power optimal design. As a result, adaptive power and performance adjustment techniques emerged as attractive methods to improve the effective power efficiency of a device in modern design approaches. Focusing on this issue, in this paper, a novel logic family is proposed that enables tuning the transistor's effective threshold voltage after fabrication for higher speed or lower power. This method along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the workload requirement. The externally static topology of the proposed logic makes it possible to replace static circuits without requiring significant changes in the system. Experimental results obtained using 90‐nm CMOS standard technology show that the proposed logic improves the average power‐delay product by about 40% for the attempted benchmarks.     

Sinusoidal oscillators with explicit current output employing current‐feedback op‐amps

Employing a state‐variable synthesis, a number of new current‐mode oscillators with explicit current output have been derived, which can be practically implemented from commercially available current‐feedback op‐amps (CFOA). The workability of the proposed structures has been confirmed by experimental results using AD844‐type CFOAs and some sample results have been presented. Copyright © 2008 John Wiley & Sons, Ltd.     

Modelling and design considerations on CML gates under high‐current effects

In this paper, the effect of the transit time degradation of bipolar transistors on the power‐delay trade‐off in CML gates and their design is dealt with. A delay model which accounts for the transit time increase due to the high bias current values used in high‐speed applications is derived by generalizing an approach previously proposed by the same authors (IEEE Trans. CAD 1999; 18 (9):1369–1375; Model and Design of Bipolar and MOS Current—Mode Logic (CML, ECL and SCL Digital Circuits), Kluwer Academic Publisher: Dordrecht, 2005). The resulting closed‐form delay expression is achieved by properly simplifying the SPICE model, and has an explicit dependence on the bias current which determines the power consumption of CML gates. Accordingly, the delay model is used to gain insight into the power‐delay trade‐off by considering the effect of the transit time degradation in high‐speed designs. In particular, the cases where such effects can be neglected are identified, to better understand how the transit time degradation affects the performance of CML gates for current bipolar technologies. The proposed model has a simple and compact expression, thus it turns out to be suitable for pencil‐and‐paper evaluations, as well as fast timing analysis. Simulations of CML circuits with a 20‐GHz bipolar process show that the model has a very good accuracy in a wide range of current and loading conditions. Copyright © 2005 John Wiley & Sons, Ltd.     

Innovative design methodologies in quantum‐dot cellular automata

Current transistor‐based IC fabrication technology faces many trivial issues such as those of excess power dissipation, expensive fabrication and short channel effects at very low device size [1]. Quantum‐dot cellular automata (QCA)‐based digital electronics on the other hand provide scope for further development in the future by shrinking the device size. Current QCA logic circuits are based on logic synthesis using Inverters and (three or five input) Majority Gates. In this paper, a new design methodology has been described that can be used to create circuits with even greater device substrate densities than what are currently achieved in existing QCA designs. Based on the proposed methodology, a new QCA inverter is proposed. It is further tested through simulations on QCA Designer. Through the simulations, it is subsequently proved to be much more reliable and robust than the presently used common QCA inverter(s). In the second section of this paper, simple QCA circuits such as ring oscillators using odd number of inverters in daisy chains are described and designed using the proposed inverter design. Copyright © 2013 John Wiley & Sons, Ltd.     

Parameter design of event‐driven logic controller for two‐wheeled vehicle

Programmable Logic Controllers (PLCs) are widely used in industry. In PLC‐based control systems, low‐resolution (especially ON‐/OFF) sensors are inexpensive, and actuators are commonly used because they are compatible with programming languages used in PLCs. PLC switches the actuators ON/OFF as the state of the sensor changes between ON/OFF. In designing PLC‐based systems, the design of the parameters of these sensors and actuators (e.g., position of limit switches and torque of motors) is an important problem because they affect the overall performance of the system. This problem, however, has not yet been fully discussed. In the present paper, a systematic design method for this problem is developed. The main concept is to express the model of the system as a Mixed Logical Dynamical System (MLDS) and to formulate the problem as a mathematical programming problem. The developed idea is applied to the line‐following control of a two‐wheeled vehicle. The usefulness of the proposed method is demonstrated through simulation and experiments. © 2007 Wiley Periodicals, Inc. Electr Eng Jpn, 162(2): 51–60, 2008; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20584     

Current‐mode dual‐output ICCII‐based tunable universal biquadratic filter with low‐input and high‐output impedances

A new tunable current‐mode (CM) biquadratic filter with three inputs and three outputs using three dual‐output inverting second‐generation current conveyors, three grounded resistors and two grounded capacitors is proposed. The proposed circuit exhibits low‐input impedance and high‐output impedance which is important for easy cascading in the CM operations. It can realize lowpass, bandpass, highpass, bandreject and allpass biquadratic filtering responses from the same topology. The circuit permits orthogonal controllability of the quality factor Q and resonance angular frequency ω_o, and no component matching conditions or inverting‐type input current signals are imposed. All the passive and active sensitivities are low. Hspice simulation results are based on using TSMC 0.18 µm 1P6M process complementary metal oxide semiconductor technology and supply voltages ±0.9 V to verify the theoretical analysis. Copyright © 2012 John Wiley & Sons, Ltd.     

一种改进的备自投逻辑

以110 kV及以下电压等级变电所常见的分段备用电源自投装置和进线备用电源自投装置为例,结合现场工程实际,剖析了某公司分段备投装置WBT-821A的备自投装置动作逻辑缺陷,即：其“加速备投”开入如果使用不当可能造成备投误动或者无故延长负荷停电时间。为此,分别从软件设计上提出增设控制字和从屏柜设计方面提出备投开入采用“TWJ”的改进方法,另外,详细分析了某公司的进线备投装置CSC-246 的特殊闭锁问题,指出了在实际工程实践中应注意的问题,对工程实践具有重要指导意义。     

An MTJ‐based non‐volatile flip‐flop for high‐performance SoC

The conventional magnetic tunneling junction (MTJ)‐based non‐volatile D flip‐flop (NVDFF) has a slow D‐Q delay and a tradeoff between its D‐Q delay and its sensing current. In addition, a sufficient write current cannot be obtained with the core device, since two MTJs exist in the write path and a write current degradation problem occurs due to the precharge transistors. The proposed MTJ‐based non‐volatile semidynamic flip‐flop (NVSDFF) has a semidynamic structure that ensures a fast D‐Q delay and separates the sensing circuit from the D‐Q signal path to reduce the sensing current without affecting the D‐Q delay. The proposed NVSDFF also provides a sufficient write current by merely using the core device, since only one MTJ exists in the write path. In addition, the head switch, which is added to remove the write current degradation problem, further reduces the sensing current. Thus, the proposed NVSDFF has a higher read disturbance margin than the previous NVDFF with an IO device. The HSPICE simulation results with the industry‐compatible 45 nm model parameter show that the D‐Q delay in the proposed NVSDFF is 50.5% of that of the previous NVDFF with an IO device, and the sensing current, 32.3%. In the proposed NVSDFF, the read disturbance margin is 15.9% larger than in the previous NVDFF with an IO device, and the area is 17.8% smaller. Copyright © 2012 John Wiley & Sons, Ltd.     

Analytic transient solution of SCFL logic gates

In this paper we propose the analytical solution of switching transients for SCFL logic gates. The analysis of an SCFL logic gate is carried out without linearization and can be brought back to multiple analyses of a basic cell, given by a differential pair with switching input voltages and a variable tail current, to take the effect of series‐gating into account. The differential equation for this cell is a Riccati equation, if a quadratic current–voltage relationship is used for the transistors, and it can be solved by the infinite power series method, in case of polynomial input signals. An algorithm is proposed to analyse the full transient of a complex SCFL gate. This provides a closed form expression for transient signals in terms of circuit and device parameters, that can be used for symbolic analysis or fast time‐domain numerical simulation. Some case studies are presented for SCFL gates using OMMIC ED02AH technology, and a good agreement between the proposed model and SPICE simulations using complex device models is obtained. Copyright © 2005 John Wiley & Sons, Ltd.