Process dependence of BTI reliability in advanced HK MG stacks

Bias temperature instabilities (BTI) reliability is investigated in advanced dielectric stacks. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal gate thickness favors the reduction of mobility degradations and NBTI, but, also strongly enhances PBTI, due to a complex set of reactions in the gate oxide. Trade off must be found to obtain a great trade off between device performance and reliability requirements.     

NBTI degradation effect on advanced-process 45 nm high-k PMOSFETs with geometric and process variations

Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advanced-process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engineering and laser annealing in order to achieve high on-state drain current drive performance. To explore NBTI effects on an advanced-process sub-micron device, the 45 nm high-k PMOS transistor was simulated extensively with a wide range of geometric and process variations. The device was simulated at varying thicknesses in the dielectric layer, oxide interfacial layer, metal gate and polysilicon layer. In order to observe the NBTI effect on process variation, the NBTI degradation of the 45 nm advanced-process PMOS is compared with a 45 nm PMOS device which does not employ process-induced stress and incorporates the conventional rapid thermal annealing (RTA) as compared to the laser annealing process which is integrated in the advanced-process device flow. The simulation results show increasing degradation trend in terms of the drain current and threshold voltage shift when the thicknesses of the dielectric layer, oxide layer as well as the metal gate are increased.     

ISSG及其氮化工艺对NBTI效应的改善

本文在对ISSG工艺特性简单分析的基础上讨论了ISSG氧化物薄膜的可靠性问题。讨论了ISSG工艺及其相关的氮化工艺对NBTI的改善原理。数据表明ISSG工艺及其相关的氮化工艺对NBTI效应有明显的改善作用。由于原子氧的强氧化作用,ISSG工艺中最终得到的氧化物薄膜体内缺陷少,界面态密度也比较小,氧化物薄膜的质量比较高。ISSG氮化工艺与传统炉管氧化物薄膜的氮化工艺的主要区别在于N所集中的位置不一样。ISSG工艺氮化是把等离子态的N^＋注入到多晶硅栅和SiQ2的界面,不会增加SiQ2和Si衬底的界面态,从而可以显著改善NBTI效应。而传统炉管氧化物薄膜的氮化是用NO或者N2O把N注入到SiQ2和Si衬底的界面,这样SiQ2和Si的界面态就会增加,从而增强NBTI效应。     

Time-dependent degradation due to negative bias temperature instability of p-MOSFET with an ultra-thin SiON gate dielectric

This paper presents the time-dependence of the negative bias temperature instability (NBTI) degradation of p-MOSFETs with an ultra-thin silicon oxynitride gate dielectric. The concentrations of nitrogen in the gate dielectric were approximately 3% and 10%. The device with 10% nitrogen concentration had unique time-dependent degradation characteristics due to the nitrogen enhanced NBTI effect. It degraded significantly just after application of an NBTI stress. After this initial degradation, a fast and slow degradation followed in sequence. The initial, fast, and slow degradations appear to be associated with the deep donor effect of nitrogen, the diffusion of ionic and neutral hydrogen combined with Si-H bond breaking, and the diffusion of neutral hydrogen combined with O-H bond breaking, respectively. Owing to the slow down of the NBTI degradation after the initial and fast degradations, the lifetime for the device with 10% nitrogen concentration was three times longer than that with 3% nitrogen concentration.     

NBTI product level reliability for a low-power SRAM technology

We present a methodology to investigate product level NBTI reliability for the 90 nm technology node including the correlation between transistor, circuit, and product level NBTI reliability. NBTI reliability lifetime, dielectric breakdown, and gate leakage currents pose an important limitation to the maximum applicable supply voltage across the gate oxide. Product standby currents and regulator design are highly influenced by transistor reliability. We will present product reliability data ensuring sufficient product level reliability as well as their correlation attempts to transistor level reliability data.     

Study for pulse stress NBTI characteristics degradation stress

NBTI characteristic degradation of MOSFET is still one of important reliability physics in semiconductor device. Although it is well recognized that its degradation is recovered immediately after releasing DC test stress, it is also fact that the voltage which is applied to the gate electrode in most semiconductor device is an intermittent stress like pulse, not consecutive DC stress as NBTI test. Accurate NBTI lifetime prediction method under this pulse stress condition can afford an actual reliable lifetime. In this work, we considered the characteristic recovery phenomenon in pulse NBTI stress with MOSFET of TOSHIBA 40 nm and 90 nm CMOS process technology and examined a more realistic life prediction method.     

Atomic Layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics for future high-speed DRAM with enhanced reliability

Atomic layer-deposited (ALD) Si-nitride/SiO/sub 2/ stack gate dielectrics were applied to high-performance transistors for future scaled DRAMs. The stack gate dielectrics of the peripheral pMOS transistors excellently suppress boron penetration. ALD stack gate dielectrics exhibit only slightly worse negative-bias temperature instability (NBTI) characteristics than pure gate oxide. Enhanced reliability in NBTI was achieved compared with that of plasma-nitrided gate SiO/sub 2/. Memory-cell (MC) nMOS transistors with ALD stack gate dielectrics show slightly smaller junction leakage than those with plasma-nitrided gate SiO/sub 2/ in a high-drain-voltage region, and have identical junction leakage characteristics to transistors with pure gate oxide. MCs having transistors with ALD stack gate dielectrics and those with pure gate oxide have the identical retention-time distribution. Taking the identical hole mobility for the transistors with ALD stack gate dielectrics to that for the transistors with pure gate oxide both before and after hot carrier injection (previously reported) into account, the ALD stack dielectrics are a promising candidate for the gate dielectrics of future high-speed, reliable DRAMs.     

28 nm PMOS器件中Ge注入对NBTI可靠性的影响

研究了28 nm 多晶硅栅工艺中Ge注入对PMOS器件的负偏压温度不稳定性(NBTI)的影响。在N阱中注入Ge,制作了具有SiGe沟道的PMOS量子阱器件。针对不同栅氧厚度和不同应力条件的器件,采用动态测量方法测量了NBTI的退化情况,采用电荷泵方法测量了界面态的变化情况。实验结果表明,由于Ge的注入,PMOS器件中饱和漏电流的退化量降低了43%,同时应力过程中产生的界面态得到减少,有效提高了PMOS器件的NBTI可靠性。     

影响PMOSFET中NBTI效应的相关因素研究

在PMOSFET上施加负栅压和高温应力后，出现的NBTI效应是超深亚微米MOS器件中重要的可靠性问题之一。研完了NBTI效应对PMOSFET器件参数的影响及其产生机理；基于NBTI效应的产生模型，分析了Si／SiO2界面处氢、氮和水等相关因素对NBTI效应的影响；介绍了减小NBTI效应的方法。     

Reliability of ultrathin nitrided oxides grown in low pressure N2O ambient

The influence of N₂O oxynitridation and oxidation pressure on reliability of ultrathin gate oxides from 4 down to 2.5 nm thickness was investigated. A set of different oxidation parameters was applied during oxide growth which comprised oxidation pressure and N₂O partial pressure during rapid thermal oxidation. The reliability of the oxides was tested by constant voltage stress. Evaluation of the resulting times to soft breakdown (t_sbd) for different stress voltages allows to predict a supply (gate) voltage V^10y,max providing an oxide lifetime of 10 years. For this extrapolation, t_sbd was assumed to increase exponentially as stress voltage is reduced. The slope of the extrapolation is found to become steeper as oxides become thinner, which implies higher V^10y,max and thus higher reliability for thinner oxides as under an assumption of a uniform slope for all thicknesses. Further, the results of this extrapolation demonstrate that oxidation in N₂O containing ambient can improve oxide reliability for ultrathin gate oxides.     

Influence of various process steps on the reliability of PMOSFETs submitted to negative bias temperature instabilities

In this paper, we analyze the impact of various process steps on the reliability of PMOSFET’s submitted to Negative Bias Temperature Instabilities stress conditions. We give some evidence of the complete thermal anneal of interface states induced by NBTI and investigate the influence of the oxide thickness and of the final forming gas anneal. Then we show a NBTI lifetime improvement after a fluorine implant through the gate and an arsenic bulk doping value increase.     

超深亚微米PMOSFET器件的NBTI效应

研究了超深亚微米PMOS器件中的NBTI(负偏置温度不稳定性)效应,通过实验得到了NBTI效应对PMOSFET器件阈值电压漂移的影响,并得到了在NBTI效应下求解器件阈值电压漂移的经验公式.分析了影响NBTI效应的主要因素:器件栅长、硼穿通效应和栅氧氮化以及其对器件寿命退化的作用.给出了如何从工艺上抑制NBTI效应的方法     

pMOS器件NBTI界面电荷引起耦合的数值模拟分析

从二维模拟pMOS器件得到沟道空穴浓度和栅氧化层电场,用于计算负栅压偏置温度不稳定性NBTI(Negative bias temperature instability)效应的界面电荷的产生,是分析研究NBTI可靠性问题的一种有效方法。首先对器件栅氧化层/硅界面的耦合作用进行模拟,通过大量的计算和已有的实验比对分析得出:当NBTI效应界面电荷产生时,栅氧化层电场是增加了,但并没有使界面电荷继续增多,是沟道空穴浓度的降低决定了界面电荷有所减少(界面耦合作用);当界面电荷的产生超过1012/cm2时,界面的这种耦合作用非常明显,可以被实验测出;界面耦合作用使NBTI退化减小,是一种新的退化饱和机制,类似于"硬饱和",但是不会出现强烈的时间幂指数变化。     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

NBTI degradation in STI-based LDMOSFETs

NBTI degradation in STI-based LDMOSFETs has been investigated by multi-region DCIV spectroscopy (MR-DCIV), a non-destructive and sensitive method to probe the interface states on channel, accumulation and STI region. A unified MR-DCIV current model was proposed based on its independency to the forward bias and temperature. Under the same negative gate stress condition, MR-DCIV current degradation was compared for nLDMOSFET and pLDMOSFET. Much larger MR-DCIV current shift was observed at channel and accumulation region with thin gate oxide thickness, indicating interface states generation at related regions. Our results show that more significant degradation for multi-finger device was consistent with NBTI degradation mechanism. High voltage device design with thermal management consideration is of crucial importance to guaranteeing the device performance and reliability.     

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide range of gate-leakage and NBTI stress data from a variety of plasma-oxynitride gate dielectric devices to establish an optimization scheme for gate-leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process and IC design.     

Influence of I/O oxide process on the NBTI performance of 28 nm HfO2-based HKMG p-MOSFETs

The NBTI (negative bias temperature instability) performance of 28 nm HfO₂-based HKMG (high-κ metal gate) I/O thick oxide p-MOSFETs with different I/O oxide processes is reported. The results show that the NBTI performance from ISSG (in-situ steam generation) process is better than that from the furnace Gox1 process. The NBTI dependence on the PDA (post deposition anneal) process is studied and we show that PDA can significantly improve NBTI. We investigate the influence of DPN (decoupled plasma nitridation) on NBTI; the NBTI performance from the DPN process is much better than that from non-DPN processes for the devices with the same EOT (electrical oxide thickness). Based on the experiments, we propose an extended NBTI model, which incorporates nitrogen concentration in the formula for the process with DPN. This extension provides much clearer direction on process tuning to better control the DPN dosage and the EOT to meet both process electric and reliability requirements.     

A New NBTI Model Based on Hole Trapping and Structural Relaxation in MOS Dielectrics

Negative bias temperature instability (NBTI) is one of the major reliability concerns for analog and digital MOS devices. NBTI understanding and modeling is receiving a growing interest for failure prediction, depending on the temperature and duty cycle of dynamic-stress conditions. In this framework, we present a new NBTI model based on hole trapping and thermally activated relaxation. The model unifies previous concepts of hole tunneling/trapping and structural relaxation initiated by hole trapping. Simulation results can account for the time and temperature dependence of NBTI stress, NBTI recovery, and the dependence on thickness and nitridation technology of the gate dielectric. The numerical model may be used for physics-based reliability predictions of NBTI effects as a function of time, temperature, and stress regime.      

Evidence for two distinct positive trapped charge components in NBTI stressed p-MOSFETs employing ultrathin CVD silicon nitride gate dielectric

Besides the generation of interface states and the associated positive trapped charge (N/sub tc1/), experimental results unambiguously show the generation of another positive trapped charge component (N/sub tc2/) during negative-bias temperature instability (NBTI) stressing of p-MOSFETs employing ultrathin silicon nitride gate dielectric. For a given gate stress voltage, N/sub tc2/ is generated at a much faster rate compared to N/sub tc1/. Under the pulsed gate condition studied, N/sub tc1/ could almost be completely annihilated, regardless of the NBTI stress voltage, whereas only partial annihilation of N/sub tc2/ is observed. This more resistant nature of N/sub tc2/ to post-stress relaxation has serious implications on the dynamic NBTI reliability of these p-MOSFETs.     

高压pLEDMOS器件在不同应力条件下导通电阻的衰退及改进方法

实验测试结果揭示高压pLEDMOS器件在不同的应力条件下,导通电阻的衰退结果不同,半导体器件专业软件MEDICI模拟结果表明Si/SiO2表面的陷阱产生以及热电子的注入和俘获导致了高压pLEDMOS器件在不同的应力条件下产生不同的导通电阻衰退.文中同时提出了一种改进方法:用场氧代替厚栅氧作为高压pLEDMoS器件的栅氧,MEDICI模拟结果显示该方法可以明显降低/减缓高压pLEDMOS导通电阻的衰退.