Multi-physics reliability simulation for solid state lighting drivers

This paper is introducing a multi-physics reliability simulation approach for solid state lighting (SSL) electronic drivers. This work explores the system-level degradation of SSL drivers by means of applying its components reliability information into a system level simulation. Reliability information of the components such as capacitor, and inductor, defines how a component electrical behavior changes with temperature, and also with time. The purpose of this simulation is to understand the thermal–electrical behavior of SSL electronic drivers through their lifetime. Once the behavior of the device during its lifetime is understood, the real cause of the failure can be distinguished and possibly solved.     

Influence of dicing damages on the thermo-mechanical reliability of bare-chip assemblies

Increased demands for the integration density of electronics initiate a turnaround in packaging technologies, away from packaged constructions towards bare-chip-assemblies. A particular challenge of using bare-chips is the avoidance of chip fracture during processing and subsequent use. In this study a comprehensive portfolio of methods to predict the risk of chip fracture for bare-chips is shown. The basis is an investigation on the influences of different dicing techniques on the breaking strength of silicon chips. The stress resistivity of the chips shows huge differences, for instance 110 MPa after diamond-scribing up to 1473 MPa after thermal-laser-separation. Additionally, damages induced by the dicing were studied using scanning electron microscopy. The analysis of the size effect of diced silicon chips enabled to calculate the scaling parameter which is a size and stress independent strength value. All obtained results were used to develop a probabilistic reliability model for bare-chip-assemblies which describes the risk of chip fracture during the die attachment.     

单片机虚拟实验中仿真电路的建立方法

本文主要讨论在以教学为目的的单片机虚拟实验仿真软件设计过程中仿真电路的建立方法。提出了一种以VC＋＋为平台,完全使用仿真软件实现单片机虚拟实验教学的思想。阐述了仿真元件、元件基本操作、元件连接、电路状态跟踪的设计以及电路初始状态的计算。     

单片机虚拟实验中仿真电路的建立方法

本文主要讨论在以教学为目的的单片机虚拟实验仿真软件设计过程中仿真电路的建立方法。提出了一种以VC++为平台,完全使用仿真软件实现单片机虚拟实验教学的思想。阐述了仿真元件、元件基本操作、元件连接、电路状态跟踪的设计以及电路初始状态的计算。     

An EMC-oriented VHDL-AMS simulation methodology for dynamic current activity assessment

Dynamic current activity extraction plays a very important role in estimating the electromagnetic compatibility of integrated circuits. For that purpose, the Integrated Circuit Electromagnetic Model (ICEM) is being developed by the International Electrotechnical Commission (IEC). This article introduces a mixed-mode simulation methodology, based on the VHDL-AMS language, which dramatically reduces simulation times while taking into account various circuit activities. The use of such a methodology in the case of SRAM memories is described, allowing the definition of an ICEM-compatible intellectual-property (IP) dynamic activity model aimed at emission level prediction.     

A methodology for reliability analysis in health networks

A reliability model for a health care domain based on requirement analysis at the early stage of design of regional health network (RHN) is introduced. RHNs are considered as systems supporting the services provided by health units, hospitals, and the regional authority. Reliability assessment in health care domain constitutes a field-of-quality assessment for RHN. A novel approach for predicting system reliability in the early stage of designing RHN systems is presented in this paper. The uppermost scope is to identify the critical processes of an RHN system prior to its implementation. In the methodology, Unified Modeling Language activity diagrams are used to identify megaprocesses at regional level and the customer behavior model graph (CBMG) to describe the states transitions of the processes. CBMG is annotated with: 1) the reliability of each component state and 2) the transition probabilities between states within the scope of the life cycle of the process. A stochastic reliability model (Markov model) is applied to predict the reliability of the business process as well as to identify the critical states and compare them with other processes to reveal the most critical ones. The ultimate benefit of the applied methodology is the design of more reliable components in an RHN system. The innovation of the approach of reliability modeling lies with the analysis of severity classes of failures and the application of stochastic modeling using discrete-time Markov chain in RHNs.     

Reliability simulation for analog ICs: Goals,solutions, and challenges

The need for new tools and simulation methodologies to evaluate the impact of all reliability effects in ICs is a critical challenge for the electronic industry. Issues due to process-related variations (also known as spatial variability) are well-known and off-the-shelf simulation methods are available. On the other hand, models and simulation methods for the aging-related problems, which are becoming more important with each technology node, are far less mature, specially for analog ICs. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) cause a time-dependent variability that occurs together with the spatial variability. A fundamental missing piece in the design flow is an efficient and accurate simulation methodology for IC reliability. To this goal, several challenges should be addressed properly: the essential nature of the stochastic behavior of aging (and thus resorting to stochastic models rather than deterministic ones), the correlation between spatial and aging-related variability, and relationship between biasing, stress and aging in analog ICs, among others. This paper discusses some of these challenges in detail.     

A low-overhead and reliable switch architecture for Network-on-Chips

This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation of the erroneous flits in NoC is prevented without any need to credit signals and, retransmission buffers. Using an HDL-based NoC simulator, the LRS is compared to two other widely used reliability enhancement methods: the Switch-to-Switch (S2S) and the End-to-End (E2E) methods. The simulation results show that the LRS consumes less power and provides higher performance compared to those of the E2E and S2S methods. More importantly, unlike the E2E and the S2S methods, the LRS has constant overheads, which makes it applicable in all working conditions. To validate the comparison, an analytical performance and reliability model is developed for the LRS, S2S and E2E methods. The results of the model match those obtained from the simulations while the proposed model is significantly faster.     

A simulation approach for computing systems reliability

The basis of the concept of reliability is that a given component has a certain stress-resisting capacity; if the stress induced by the operating conditions exceeds this capacity, failure results. Most of the published results in this area are based upon analytical modelling of stress and strength, using various probability distributions, and then trying to find an exact expression for system reliability, which can be very difficult to obtain sometimes. The approach used in this paper is very simple and uses simulation techniques to repeatedly generate stress and strength of a system by the computer, using a random number generator and methods such as the inverse transformation technique. The advantage of this approach is that it can be used for any stress-strength distribution functions. Finally, numerical results obtained from using this approach are compared with results obtained using the analytical methods for various strength-stress distribution functions, such as exponential, normal, log normal, gamma and Weibull. Results show the viability of the simulation approach.     

Design methodology for full custom CMOS microcomputers

A highly structured design methodology is necessary to be successful in the design of VLSI integrated circuits with more than 100000 transistors on a chip. Such a methodology is described: it is based on the regularity of the circuit architecture with an associated chip floor plan and on a new layout technique named metal oriented layout.This methodology has been tested with the design of a 13500 MOS microcomputer. From the instruction set and through different levels of instruction interpretation, the architecture and associated chip floor plan are generated. The detailed logic design is made directly in symbolic layout with the chip floor plan in mind.The proposed design methodology can be best appreciated by the short development time and small chip area required for the designed 13500 MOS microcomputer.     

A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level

In the past few years, Time-Dependent Variability has become a subject of growing concern in CMOS technologies. In particular, phenomena such as Bias Temperature Instability, Hot-Carrier Injection and Random Telegraph Noise can largely affect circuit reliability. It becomes therefore imperative to develop reliability-aware design tools to mitigate their impact on circuits. To this end, these phenomena must be first accurately characterized and modeled. And, since all these phenomena reveal a stochastic nature for deeply-scaled integration technologies, they must be characterized massively on devices to extract the probability distribution functions associated to their characteristic parameters. In this work, a complete methodology to characterize these phenomena experimentally, and then extract the necessary parameters to construct a Time-Dependent Variability model, is presented. This model can be used by a reliability simulator.     

Design concept for wire-bonding reliability improvement by optimizing position in power devices

The most effective way to increase the reliability of wire bonds in IGBT modules is reduction of temperature difference between the aluminum wires and the device. However, this lowers the power handling capability of the modules. In this paper, we show that the configuration of aluminum wire bonds on power devices has a considerable effect on the temperature distribution of the device, and that the optimization of the layout by thermo-electric simulation can make the temperature distribution of the devices more uniform and consequently reduce the maximum junction temperature difference, ΔT_jmax. Tentative experiments showed that rearranging the bonding position resulted in reduction of ΔT_jmax by five to 8 °C, and that the chip temperature distribution estimated by the thermo-electric simulation was qualitatively similar to the actual measurement results. These results suggest that wire-bonding optimization by thermo-electric simulation can contribute not only to realizing more compact power modules but also to improving the module reliability.     

RELVEC — a tool for control system reliability analysis

This article will present a computerized reliability analysis tool for large control systems. It will also show a new dynamic representation of system structure. It enables us to model the physical system only once for any number of control tasks. The algorithm for computing minimal cut sets for the control tasks has been developed and automated. The result is RELVEC, an interactive computer program that performs reliability/availability calculation, sensitivity analysis and critical component identification. It can handle two repair policies and common mode failures. Reconfiquring of the physical system or the control tasks is simple. RELVEC is becoming an everyday tool in control system reliability analysis at VTT.     

A novel GAAC FinFET transistor: device analysis, 3D TCAD simulation, and fabrication

We report the analysis and TCAD results of a gate-all-around cylindrical (GAAC) FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinite number of gates surrounding the cylinder-shaped channel. The symmetrical nature of the field in the channel leads to improved electrical characteristics, e.g. reduced leakage current and negligible corner effects. The Ion/Ioff ratio of the device can be larger than 106, as the key parameter for device operation. The GAAC FinFET operating in accumulation mode appears to be a good potential candidate for scaling down to sub-l0 nm sizes.     

一种新型的圆柱体全包围栅结型场效应管体管： 器件物理, 器件仿真, 器件工艺

We report the analysis and TCAD results of a gate-all-around cylindrical （GAAC） FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinite number of gates surrounding the cylinder-shaped channel. The symmetrical nature of the field in the channel leads to improved electrical characteristics, e.g. reduced leakage current and negligible corner effects. The Ion/Ioff ratio of the device can be larger than 106, as the key parameter for device operation. The GAAC FinFET operating in accumulation mode appears to be a good potential candidate for scaling down to sub-10 nm sizes.     

A Performance Driven Lot Merging Method with Closed Loop Optimization for Semiconductor Wafer Fabrication

This paper deals with lot merging problem in semiconductor wafer fabrication system.There is the possibility to merge two or more partial lots into single lot if their subsequent process routes are the same,an improved lot merging method is presented by grouping lots belonging to different orders.Based on job information extracted from the buffers,several bin packing and knapsack solving algorithms are used to determine which lots should be merged.An iterative improvement procedure is introduced for optimizing merging strategy through a heuristic algorithm with resetting the ready time of critical lots.The closed loop structure with global revision factor is built for minimizing the impact of uncertain events while balancing the different orders processing progress.Applied to a simulation semiconductor manufacturing fab,the proposed algorithm can reduce cycle time and tardiness compared with other methods currently.     

一种小型化移动终端全网通天线

小型化是进行5G微基站天线设计的重要考虑因素,文中设计了一款适用于5G微基站的电磁偶极子天线. 天线由一对正交放置的单极化电磁偶极子、一对交叉放置的渐变式Γ形馈电线、一个圆形寄生贴片和一块正方形反射板组成,工作频段为2.50~3.62 GHz和4.8~5.0 GHz,能够覆盖工信部规定的5G的全部中频段. 在工作频带内,天线的输入回波损耗小于−10 dB;端口隔离度在低频段小于−25 dB,在高频段小于−42 dB;仿真平均增益在高、低频部分分别为5.57 dBi和9.84 dBi. 该天线能够实现双频段和双极化,可以作为小型化微基站天线设计的参考,同时为5G天线的商用化提供参考.     

一种小型化移动终端全网通天线

提出一款适用于移动终端设备的小型化全网通天线, 天线由参考地和平面天线构成, 采用同轴馈电.该天线的高频通带响应通过高频单元基模与低频单元分支的高次模实现, 天线的低频通带响应通过低频单元基模实现, 并采用展宽低频单元枝节的方法实现所需低频通带带宽.天线总尺寸为30 mm×67 mm, 其中辐射单元为33 mm×30 mm, 参考地大小为34 mm×30 mm.使用微波仿真软件HFSS对天线的尺寸进行了设计优化, 并对回波损耗、天线表面电流和天线的辐射方向图进行研究.天线样品的实测-6 dB阻抗带宽为820~968 MHz, 1 695 ~3 020 MHz, 覆盖了工信部所颁布的国内移动通信运营商所用的2G、3G、4G网络的全部频段.天线结构简单、覆盖频率广、体积小, 具有一定的工程应用价值.     

A methodology for predicting service life and design of reliability experiments

This paper summarizes a methodology for reliability prediction of new products where field data are sparse, and the allowed number & length of experiments are limited. The methodology relies on estimating a set where the unknown parameters are most likely to be found, calculation of an upper bound for the reliability metric of interest conditioned that the parameters reside in the estimated set, and tightening the bounds via design of experiments. Models of failure propagation, failure acceleration, system operations, and time/cycle to failure at various levels of fidelity & expert elicited information may be incorporated to enhance the accuracy of the predictions. The application of the model is illustrated through numerical studies.