Error suppression techniques for energy-efficient high-resolution SAR ADCs

The successive approximation register (SAR) is one of the most energy-efficient analog-to-digital converter (ADC) architecture for medium-resolution applications. However, its high energy efficiency quickly diminishes when the target resolution increases. This is because a SAR ADC suffers from several major error source, including the sampling kT/C noise, the comparator noise, and the DAC mismatch. These errors are increasing hard to address in high-resolution SAR ADCs. This paper reviews recent advances on error suppression techniques for SAR ADCs, including the sampling kT/C noise reduction, the noise-shaping (NS) SAR, and the mismatch error shaping (MES). These techniques aim to boost the resolution of SAR ADCs while maintaining their superior energy efficiency.     

一种用于逐次逼近ADC的高能效高线性度开关电容时序

提出了一种用于逐次逼近模数转换器的高能效高线性度开关电容时序。相较于典型的基于V_CM的开关原理,该开关时序可减少37%的开关能量,并具有更高的线性度。该开关时序已应用于1V,10位300kS/s的SAR ADC,并在0.18μm标准CMOS工艺下成功流片。测试结果表明,在1V电源电压下,此SAR ADC的SNDR为55.48dB,SFDR为66.98dB,功耗为2.13μW,品质因数到达14.66fJ/c-s。DNL和INL分别为0.52/-0.47 LSB和0.72/-0.79 LSB,并且与静态非线性模型一致,最大INL出现在 V_FS/4处和3V_FS/4处。     

Energy-efficient CMOS delay line with self-supply modulation for low-power SAR ADCs

ABSTRACT

A new digital delay line based on the inverter chain is proposed. The proposed new method of connection of the inverters allows much longer delay times to be achieved for the same number of transistors, the same amount of power to be consumed as for conventional connection of inverters. Simulation results using a 65 nm CMOS design kit from ST Microelectronics are provided. An application example of the proposed delay line is provided for low-power, low-speed successive approximation register (SAR) analogue-to-digital converters (ADC).     

Passive reference-sharing SAR ADC

Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used for their simple architecture, inherent low-power consumption and small footprint. Several techniques aiming to reduce the power consumption, to increase the speed, and to reduce the capacitance spread have been developed, such as splitting the digital-to-analog converter (DAC) capacitor array, and charging and discharging the DAC capacitors in multiple steps. In this paper, a fully differential, low-power, passive reference voltage sharing SAR ADC architecture is presented, along with its theoretical analysis and test results. In this architecture, suitable for low sampling rate and low-resolution applications, the reference voltage is scaled down by successively connecting equally sized capacitors in parallel, allowing the use of small capacitor for its implementation. The implemented 6-bit ADC is one of the smallest ADCs reported in a 180-nm technology, and features a FoM between 30.8 and 39.3 fJ per conversion step without considering the clock generator power consumption.     

A new successive approximation architecture for high-speed low-power ADCs

A new high-speed successive approximation analog-to-digital converter (ADC) architecture is presented. Two-bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two digital-to-analog converter (DACs), is another novelty of the new architecture. The proposed DAC structure allows a substantial reduction in overall control logic complexity. A 10-bit 40 Ms/S successive approximation ADC was designed based on the proposed architecture in CMOS technology. The simulation results show that the proposed architecture introduces 7% reduction in power consumption over conventional architecture. Furthermore, chip area for the new ADC is 40% less than what otherwise would be needed by an ADC using conventional architecture.     

一种精度可编程的低功耗SAR ADC

设计了一种精度可编程的低功耗逐次逼近型模数转换器(SAR ADC)。采用电阻电容混合结构的数模转换(DAC)阵列,通过对低位电阻阵列的编程控制,实现了12,0,8位的转换精度,对应不同的精度,电路支持1,5,10 MS/s的转换速率。采用一种改进的单调开关控制逻辑以降低功耗和面积,同时避免了原有单调开关逻辑存在信号馈通的缺点。根据不同的精度要求,对比较器所用预放大器的个数进行编程控制,进一步提高了ADC的功耗效率。电路基于0.18 μm的CMOS工艺设计,在1.8 V电源电压下,精度从高到低对应的功耗分别为0.56,0.48,0.42 mW;SNDR分别为73.2,61.3,48.2 dB;SFDR分别为96.3,84.6,62.8 dB。芯片内核面积仅为(0.6×0.9)mm²,适用于通用片上系统(SoC)。     

一种10bit双通道流水线SAR ADC设计

为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型（SAR）模数转换器（ADC）。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm2。ADC的微分非线性和积分非线性分别小于0.36 最低有效位（LSB）和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 MS/s。运行频率为230 MS/s和260 MS/s的ADC的功率消耗分别为13.9 mW和17.8 mW。     

11有效位数，精度可编程且非校正的时间模式逐次逼近模数转换器

设计了一种10或者12位的可编程差分逐次逼近模数转换器,用于桥梁应力监测系统。该模数转换器采用了一种新颖的时域比较器,且提出了几种提高时域比较器精度的技术。该芯片在UMC 0.18um工艺上实现。当模数转换器工作于12位模式100K采样率时,输入47.7kHz正弦波时, 有效位数为11,无杂散动态范围为77.48dB, 最大微分非线性为0.2/-0.74LSB,最大积分非线性为 1.27/-0.97LSB,总功耗为558uW。     

逐次逼近型模数转换器的仿真模型

首先分析了构建ADC模型的2个关键环节:如何用数字量函数替代实际的模拟量输入,以及如何构建仿真模型内核。利用线性插值算法实现了环节一,并以逐次逼近型ADC为例,构建了模型的仿真内核。为了更加清晰地表述这种ADC模型的作用,以"有采样保持器"和"无采样保持器"为例,通过实际的ADC模型算例分析了无采样保持器对ADC转换结果的影响,客观表现出这种模型的开放性和广泛适用性。     

On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs

This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μ W, while the digital part consumes only 203 μ W.     

A 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information

This paper presents a 7-bit 15 × interleaved SAR ADC that operates up to 3 GS/s, using 180 nm CMOS technology. The ADC utilizes the transient information of a dynamic SAR voltage-comparator to resolve 2 bits per clock cycle, using a time-comparator block. Thus, only 5 clock cycles are needed to resolve 7 bits. This results in speed improvement of about 60%, compared to conventional ADC. Also, an improved Quasi C-2 C DAC structure with reduced internal node swing and reduced switching activity are utilized, which decreases the power consumption of DAC up to 65%. We employ the above techniques in designing a 7-bit SAR ADC, in which 3 bits are resolved with time-comparator blocks and 4 bits are resolved with a voltage-comparator. To calibrate the proposed time-comparator block, a calibration process is proposed. ADS simulation of the ADC illustrates an ENOB (Effective Number of Bits) > 6.5-bit and SFDR (Spur Free Dynamic Range) = −52.8 dBc for a single SAR converter with sampling at 200 MS/s. For the time-interleaved SAR ADC with 15 single SAR converters, ENOB is 6.15-bit and SFDR = −45 dBc with sampling at 3 GS/s up to Nyquist frequency. This ADC consumes 150 mW at 1.8 V supply and achieves a Figure-of-Merit (FoM) of 700 fJ/conv-step.     

一种基于电压窗口技术的超低功耗SAR ADC

本文提出了一种应用于生物医学的超低功耗逐次逼近型模数转换器(SAR ADC).针对SAR ADC主要模块进行超低功耗设计.数模转换(DAC)电路采用vcm-based以及分段电容阵列结构来减小其总电容,从而降低了DAC功耗.同时提出了电压窗口的方法在不降低比较器精度的情况下减小其功耗.此外,采用堆栈以及多阈值晶体管结构来减小低频下的漏电流.在55nm工艺下进行设计和仿真,在0.6V电源电压以及l0kS/s的采样频率下,ADC的信噪失真比(SNDR)为73.3dB,总功耗为432nW,品质因数(FOM)为11.4fJ/Conv.     

线性限幅器的设计与研究

ADC芯片广泛用于现代无线电系统,已成为大量军事装备中不可或缺的部分。复杂电磁环境可导致接收机灵敏度下降甚至失效。接收机用的ADC 芯片耐受大信号能力有限,急需一种既能保证其正常工作,又不会影响其采样灵敏度的器件,为此开发了一种新的器件,线性限幅器。为满足高线性度的限幅要求,介绍了一种基于PIN二极管的小型化线性限幅器设计方案。用ADS 仿真设计,薄膜混合工艺、一体化陶瓷管壳装配实现,开发出了一系列频率覆盖10 MHz~5 GHz,尺寸仅5 mm×5 mm×2.5 mm 的高线性度限幅器。测试结果表明,P 波段300~500 MHz产品损耗小于0.6 dB,输出P-1 大于11 dBm,输入0 dBm 信号时OIP3 大于35 dBm,输入25 dBm 信号时漏功率低于12 dBm,最大可承受功率5 W。ADC 芯片的可靠性大大提高,具有广阔应用前景。     

两种流水折叠分级式ADC及其结构比较

 本文利用模拟余量和模拟余差研制出两种流水折叠分级式ADC,提出了两种电路改进结构——有余差转换和无余差转换,并通过动态性能的测试来对比分析两结构的优缺点.无余差转换的ADC+和由其复合构成的ADC的测试表明,性能分别达到2bits@40MSPS ADC+和2+8bits@40MSPS ADC.对于实际制作的ADC电路,具体给出了结构图以及动态性能测试图.     

High-resolution background calibrated ADCs for software-defined radios

Next-generation transceivers operating with different standards require the existence of a wide bandwidth and highly linear analog-to-digital converters (ADCs) to enable software-defined radios (SDR). Several methods dealing with the design and implementation of high-resolution and high-speed ADCs to provide the stringent requirements of the wide-bandwidth transceivers are presented. A special focus is made on pipelined ADC for its superior performance in terms of speed and resolution. A digital background calibration technique to compensate for the capacitors mismatch, and the finite opamps gain is presented. Low overhead digitally oriented technique to increase the speed of the ADC beyond the technological limits by overcoming the problems of the conventional time-interleaving is also presented. Simulation results prove the effectiveness of these techniques.     

A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm², including the TI ADC core and memory.     

A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS

A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65 nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are −0.4/0.4 LSBs and −0.9/0.8 LSBs, respectively. At 660 MS/s sampling rate, the ADC consumes 7.6 mW from a 1.2 V supply. The proposed SAR ADC?s SNDR and SFDR are 49.5 dB and 64.2 dB, respectively.     

超低功耗逐次逼近寄存器型模数转换器的设计

采用逐次逼近方式设计了一个12 bit的超低功耗模数转换器(ADC).为减小整个ADC的芯片面积、功耗和误差,提高有效位数(ENOB),在整个ADC的设计过程中采用了一种改进的分段电容数模转换器(DAC)阵列结构.重点考虑了同步时序产生电路结构,对以上两个模块的版图设计进行了精细的布局.采用0.18 μm CMOS工艺,该ADC的信噪比(SNR)为72 dB,有效位数(ENOB)为11.7 bit,该ADC的芯片面积只有0.36 mm2,典型的功耗仅为40 μW,微分非线性误差小到0.6 LSB、积分非线性误差只有0.63 LSB.整个ADC性能达到设计要求.     

一种8通道12位逐次逼近式A/D转换器的设计

设计实现了一个8通道12位逐次逼近式A/D转换器。A/D转换器内部集成了多路复用器和并行到串行转换寄存器、复合型D/A转换器,实现数字位的串行输出。整体电路采用HSPICE进行仿真,转换速率为133 ksps(千次采样每秒),转换时间为7.5μs。通过低功耗设计,工作电流降低为2.8 mA。芯片基于0.6μm BiCMOS工艺完成版图设计,版图面积为2.5 mm×2.2 mm。     

一种用于CMOS图像传感器的Column-Level模数转换器

设计了一种用于CMOS图像传感器(CIS)的column-level模数转换器(ADC)。它由一种新型斜坡发生器构成,具有分辨率可调的特点,而且以简单的结构实现了高精度和低功耗,占用较小的版图面积。基于0.35μm2P4M标准CMOS工艺,8bit ADC转换时间约50μs,最大线性误差小于±0.5LSB。在分辨率为640×480pixel的CIS中,每列共用1个比较器,提高了传感器的吞吐速率,帧频约40fps;3.3V电压下ADC总功耗不超过27mW,占用版图面积约0.5mm2。