A novel miniaturized power amplifier with nth harmonic suppression

In this paper, a novel miniaturized power amplifier (PA) matched by two proposed low pass filters (LPFs) with nth harmonics suppression is presented. In the proposed PA, the LPFs are employed as an output and input impedance transformer networks, which transform 50 Ω to the desired impedances. In the proposed PA the conventional output and input matching networks are eliminated, which results in 52% size reduction and 6% power added efficiency (PAE) improvement compared with the conventional PA. Moreover, using the LPFs at the output and input impressively suppress the unwanted harmonics (2nd–6th) with high level of attenuation. The proposed PA works at the 2.6 GHz, which is suitable for long term evolution (LTE) applications. The measured and simulated results are in the good agreement, which confirm the validity of the proposed method.     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

Record gain at 3.1 GHz of 4H-SiC high power RF MESFET

In this paper, a very high gain 4H-SiC power MESFET with incorporation of L-gate and source field plate (LSFP-MESFET) structures for high power and RF applications is proposed. The influence of L-gate and source field plate structures on saturation current, breakdown voltage (V_b) and small-signal characteristics of the LSFP-MESFET was studied by numerical device simulation. The optimized results showed that V_b of the LSFP-MESFET is 91% larger than that of the 4H-SiC conventional MESFET (C-MESFET), which meanwhile maintains almost 77% higher saturation drain current characteristics. The maximum output power densities of 21.8 and 5.5 W/mm are obtained for the LSFP-MESFET and C-MESFET, respectively, which means about 4 times larger output power for the proposed device. Also, the cut-off frequency (f_T) of 23.1 GHz and the maximum oscillation frequency (f_max) of 85.3 GHz for the 4H-SiC LSFP-MESFET are obtained compared to 9.4 and 36.2 GHz for that of the C-MESFET structure, respectively. The proposed LSFP-MESFET shows a new record maximum stable gain exceeding 22.7 dB at 3.1 GHz, which is 7.6 dB higher than that of the C-MESFET. To the best of our knowledge, this is 2.5 dB greater than the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

5–11 GHz CMOS PA with 158.9 ± 41 ps group delay and low power using current-reused technique

This paper proposes the design of a low group delay and low power ultra-wideband (UWB) power amplifier (PA) in 0.18 μm CMOS technology. The PA design employs two stages cascade with inductive peaking technique to provide broad bandwidth characteristic and higher gain while gain flatness can be achieved by connecting inter-stage circuit. A common gate current-reused technique is adopted at the first stage amplifier to achieve good input matching, low group delay and low power. The simulation results show that the proposed PA design has an average gain of 11.5 dB with flatness of ±0.4 dB from 5–11 GHz, while maintaining bandwidth of 4.2–12.3 GHz. An input return loss (S₁₁) less than −10.4 dB and output return loss (S₂₂) less than −9.5 dB, respectively are obtained. The PA design achieves excellent phase linearity (i.e., group delay variation) of ±41 ps and only consuming 17 mW power from 1.2 V supply voltage. A good output 1-dB compression point OP1 dB of 3.7 dBm is obtained. By using this method, the proposed design has low group delay variation and lowest power among the recently reported UWB CMOS PAs applications.     

Design of InP DHBT power amplifiers at millimeter-wave frequencies using interstage matched cascode technique

In this paper, the design of InP DHBT based millimeter-wave(mm-wave) power amplifiers(PAs) using an interstage matched cascode technique is presented. The output power of a traditional cascode is limited by the early saturation of the common-base(CB) device. The interstage matched cascode can be employed to improve the power handling ability through optimizing the input impedance of the CB device. The minimized power mismatch between the CB and the common-emitter(CE) devices results in an improved saturated output power. To demonstrate the technique for power amplifier designs at mm-wave frequencies, a single-branch cascode based PA using single-finger devices and a two-way combined based PA using three-finger devices are fabricated. The single-branch design shows a measured power gain of 9.2 dB and a saturated output power of 12.3 dBm at 67.2 GHz and the two-way combined design shows a power gain of 9.5 dB with a saturated output power of 18.6 dBm at 72.6 GHz.     

A cascode modulated class-E power amplifier for wireless communications

A cascode modulated CMOS class-E power amplifier (PA) is presented in this paper. It is shown that by applying a modulated signal to the gate of the cascode transistor the output power is modulated. The main advantage of the proposed technique is a high 35 dB output power dynamic range. The peak power added efficiency (PAE) is 35%. The concept of the cascode power control of class-E RF PA operating at 2.2 GHz with 18 dBm output power was implemented in a CMOS technology and the performance has been verified by measurements. The prototype CMOS PA is tested by single tone excitation and by enhanced data rates for GSM evolution (EDGE) modulated signal. Digital predistortion is used to linearize the transfer characteristic. The EDGE spectrum mask is met and the rms error vector magnitude (EVM) is less than 4° in the entire output power range.     

A fully integrated 23.2 dBm P1 dB CMOS power amplifier for the IEEE 802.11a with 29% PAE

A two-stage fully integrated power amplifier (PA) for the 802.11a standard is presented. The PA has been fabricated using UMC 0.18 μm CMOS technology. Measurement results show a power gain of 21.1 dB, a P_1 dB of 23.2 dBm and a P_SAT of 26.8 dBm. The PAE is 29% and it is kept high by means of several integrated inductors. These inductors present low-DC resistance and high Q characteristics. The inductors must include extra design considerations in order to withstand the high-current levels flowing through them, so that they have been called power inductors.     

Analyses of electromagnetic vibration-based generators fabricated with LTCC multilayer and silver spring-inducer

A helical spring-inducer with silver multilayer coils of a low temperature co-fire ceramic (LTCC) technology is firstly developed in this paper for an electromagnetic vibration-based meso-generator. The LTCC process integrates a 7-layer silver micro-coil into a ceramic micro-spring, which provides the potential to enhance current output because of the more compact induction coil. The generator is combined with the spring-inducer and a spacer that are made of two magnets. The device is approximately 0.58 cm³ in volume. Through coupling activity between kinematics and electromagnetism, mechanical energy is converted to electric energy in the system. There is a maximum voltage output of 52.5 mV, a maximum power output of 2.54 mW, a power density of 4.37 mW/cm³ and a normalized power density of 12.07 mW/cm³ g² (g = 9.8 m/s²) at 71.5-Hz with a 0.03-mm vibration amplitude. In addition, appropriate formulas are derived to analyze the magnetic field, the vibration spring constant and the parasitical damping coefficient for the predicted power outputs. Moreover, the analytical result follows the measured trend; the deviation is 3.9% error for voltage output and 9.7% error for power output. At last, the LTCC fabrication in the meso-generator is validated, and the modeling is feasible.     

Full passive UHF RFID Tag with an ultra-low power,small area,high resolution temperature sensor suitable for environment monitoring

An UHF RFID Tag with an ultra-low power, small area, high resolution temperature sensor which adopted double voltage-controlled oscillators (VCO) has been designed and implemented using the SMIC CMOS 0.18 μm EEPROM 2P4M process. The core area of the tag (excluding the test bounding pad) is only 756×967 μm². The power-optimized tag allows a communication range of more than 6 m from a 1 W effective radiated output power reader.     

Power performance and scalability study of AlGaAs/GaAs double-recessed pseudomorphic high electron mobility transistors on unthinned substrate for coplanar waveguide circuit applications

We have investigated the power performance and scalability of AlGaAs/GaAs Double-Recessed Pseudomorphic High Electron Mobility Transistors (DR-PHEMTs) at 10 GHz on an unthinned GaAs substrate for CoPlanar Waveguide (CPW) circuit applications. It was found that the output power varied linearly with the logarithm of the device’s gate width ranging from 200 to 1000 μm. It increased at a rate of 0.01 dB/μm. That worked out to a doubling of output power (or 3 dB) for every 300 μm increase in the gate width. Gain decreased at a rate of about 0.005 dB/μm while PAE generally improved when the gate width was increased. As for DC measurement, the maximum transconductance of the device was about 375 mS/mm at V_G = −0.5 V and V_DS = 3 V. The gate-drain breakdown voltage (BV_GD) measured was −20 V, defined at I_G = −1 mA/mm. The microwave performance of the devices was measured on-wafer using a load-pull system at a bias of V_G = −0.5 V and V_DS = 8 V. For a device with a gate width of 1 mm, its saturated CW output power, gain and PAE value at 10 GHz was 27.5 dBm (0.55 W), 8 dB and 48%, respectively. At this same set of bias conditions, the value of f_t and f_max was 40 and 80 GHz, respectively.     

A 77 GHz FMCW radar transmitter with reconfigurable power amplifier in 65 nm CMOS

A frequency modulated continuous-wave (FMCW) radar transmitter in 65 nm CMOS is presented. The transmitter consists of one FMCW signal generator, one reconfigurable power amplifier and bias circuits. FMCW chirp signal comes from a sigma-delta modulated fractional-N phase-locked loop (PLL) with an integrated digital triangle-wave generator to control the output division-ratio of the sigma-delta modulator. A four-way power combining power amplifier is employed to improve the output power with a reconfigurable output power to satisfy different detection distance requirements. The measured results show that the chirp bandwidth achieves 2 GHz, from 76 GHz to 78 GHz, and the power amplifier achieves 13.1 dBm output P1dB with 8.1% PAE. The power amplifier and FMCW signal generator consume 228 mW and 56 mW power, respectively, with a 1.0 V power supply. The core die area is only 2.6×0.88 mm².     

Effect of substrate temperature on vapor-phase self-assembly of n-octylphosphonic acid monolayer for low-voltage organic thin-film transistors

N-octylphosphonic acid (C₈PA) monolayer was self-assembled on aluminum oxide (AlO_x) from vapor in vacuum, while the substrate temperature was varied between 25 and 150 °C. The capacitance, water contact angle measurement, Fourier transform infrared (FTIR) spectroscopy, and atomic force microscopy (AFM) confirmed the presence of C₈PA on AlO_x for all growth temperatures. However, the structural and electrical properties of such monolayers depend on their growth temperature. The minimum surface roughness of 0.36 nm, the maximum water contact angle of 113.5° ± 1.4°, the lowest leakage current density of ∼10⁻⁷ A/cm² at 3 V, and the capacitance of 0.43 μF/cm² were obtained for AlO_x/C₈PA bi-layers with C₈PA deposited at 25 °C. The elevated temperature led to increased surface roughness, decreased water contact angle, increased leakage current, inferior molecular ordering, and lower molecular coverage; while the effect on the chemisorption of the phosphonate was minimal. Methyl and methylene FTIR vibrations associated with C₈PA aliphatic tails exhibited similar centre-peak wavenumbers to those observed for C₈PA monolayers assembled from solutions, presenting a viable ‘dry’ alternative to the existing solution process.     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

Alternating current-driven,white field-induced polymer electroluminescent devices with high power efficiency

A solution-processed, all-phosphor, three-color (i.e., blue, green, and red), alternating current-driven white field-induced polymer electroluminescent device (WFIPEL), with low operational voltage, high luminance, high efficiency, high color-rendering index (CRI), and excellent color-stability, was demonstrated. The devices employed poly(vinylidene fluoride–trifluoroethylene–chlorofluoroethylene) [P(VDF–TrFE–CFE)] dielectric modified by single-walled carbon nanotubes (SWNTs) to further improve the dielectric characteristics, as the insulating layer. This significantly lowers the driving voltage of the device. Moreover, hole-generation layer and electron-transporting layer with high conductivity were used to more efficiently form and confine excitons in the emissive layer. The resulting WFIPEL devices show significant improvements in performance as compared to previous reports. Specifically, the devices exhibit a low turn-on voltage of 10 V, a maximum luminance of 7210 cd m⁻², a maximum current efficiency and power efficiency of 33.8 cd A⁻¹ and 10.5 lm W⁻¹, and a CRI of 82. The power efficiency is even 10 times higher than the highest previous report (1 lm W⁻¹).     

A 1.0 V power supply, 9.3 GB/s write speed, Single-Cell Self-Boost program scheme for high performance ferroelectric NAND flash SSD

A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0 V power supply operation in Ferroelectric (Fe-) NAND flash memories. The proposed SCSB scheme only self-boosts the channel voltage of the cell to which the program voltage V_PGM is applied in the program-inhibit NAND string. The program disturb is well suppressed at the 1.0 V power supply voltage in the proposed program scheme. The power consumption of the Fe-NAND at V_CC = 1.0 V decreases by 86% compared with the conventional floating gate (FG-) NAND at V_CC = 1.8 V without the degradation of the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.7 times and the 9.3 GB/s write throughput of the Fe-NAND SSD is achieved for an enterprise application.     

An 863-870 MHz spread-spectrum FSK transceiver design for wireless sensor

Simulation results of a 863-870 MHz frequency-hopped spread-spectrum (FHSS) transceiver with binary frequency shift keying (BFSK) modulation at 20 kb/s for wireless sensor applications is presented.The transmit/receive RF front end contains a BFSK modulator, an upconversion mixer, a power amplifier (PA), and an 863-870 MHz band pass filter (BPF) at the transmitter side and a low-noise amplifier with down conversion mixer to zero-IF, a low-pass channel-select filter, a limiter and a BFSK demodulator at the receiver side. The various block parameters of the transmit/receive RF front end like noise figure (NF), gain, 1 dB compression point (P-1 dB), and IIP3 are simulated and optimized to meet low power and low cost transceiver specifications.The transmitter simulations show an output ACPR (adjacent channel power ratio) of −22 dBc, 3.3 dBm P-1 dB of PA, and transmitted power of 0 dBm. The receiver simulations show 51.1 dB conversion gain, −7 dBm IIP3, −15 dB return loss (S11), and 10 dB NF. Low power arctangent-differentiated BFSK demodulator has been chosen and the BER performance has been co simulated with the analog receiver. The complete receiver achieves a BER of 10⁻³ at 10.5 dB of EbtoNo. The transceiver simulations show an RMS frequency error of 1.45 kHz.     

Design of low power UWB LNA based on common source topology with current-reused technique

This paper presents two low power UWB LNAs with common source topology. The power reduction is achieved by the current-reused technique. The gain and noise enhancement of the proposed circuit is based on an output buffer which is used by a common source amplifier with shunt–shunt feedback. Chip1 is an adopted T-match input network of 50 Ω matching in the required band. Measurements show that the S₁₁ and S₂₂ are less than −10 dB, and the maximum amplifier gain S₂₁ gives 9.7 dB, and the noise figure is 4.2 dB, the IIP3 is −8.5 dBm, and the power consumption is 11 mW from 1.1 V supply voltage. The input matching of chip2 is adopted from a LC high pass filter and source degenerated inductor. The output buffer with the RC-feedback topology can improve the gain, increase the IIP3, restrain the noise, improve the noise figure and decrease the DC power dissipation. Measurements show 13.2 dB of power gain, 3.33 dB of noise figure, and the IIP3 is −3.3 dBm. It consumes 9.3 mW from 1.5 V supply voltage. These two chips are implemented in a 0.18 μm TSMC CMOS process.     

Post-process thermal treatment for microwave power improvement of AlGaN/GaN HEMTs

The effects of post-process rapid thermal annealing (RTA) treatment after device fabrication on direct current, microwave and power performances of AlGaN/GaN high electron mobility transistors (HEMTs) with a gate-length of 0.2 μm were fully investigated. By 3 min post-process RTA treatment at 350 °C under N₂ atmosphere, the direct current (DC), radio frequency (RF) small signal and power performances of AlGaN/GaN HEMTs have been much improved. The output power, power gain and power added efficiency (PAE) of GaN HEMT device with gate wide of 1 mm increase from 37.09 dBm, 6.09 dB and 42.79% to 38.22 dBm, 7.22 dB and 67.3%. The post-process RTA after device fabrication has two merits. On the one hand, it improves passivation effect of SiN_x dielectric layer on AlGaN/GaN HEMT surface, suppressing RF current dispersion. On the other hand, it helps recover dry-etch damage at the Schottky metal/AlGaN interface, leading to reduction of reverse Schottky leakage current.     

Measurement of second-order nonlinear optical susceptibility of cBN crystal synthesized at high pressure and high temperature

We demonstrate a transverse electro-optical modulator based on a tiny and irregular octahedral wafer of cubic boron nitride (cBN) crystal that is prepared by hexagonal boron nitride at high pressure and high temperature using nitride as the catalyst. A continuous wave semiconductor laser at the wavelength of 650 nm is used as a light source. A novel electrode fabrication is designed, a developed method different from the conventional transverse electro-optical modulator is introduced and the expression of the intensity of output beam is thought over. We obtain the half-wave voltage based on experiments of transverse electro-optical modulation. The second-order nonlinear optical susceptibility χ_ijk⁽²⁾(ω,0)=1.919×10⁻¹² m/V of cBN crystal is calculated by means of the half-wave voltage.