Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlN_x) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlN_x) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.     

Thin reduced graphene oxide interlayer with a conjugated block copolymer for high performance non-volatile ferroelectric polymer memory

Polymer ferroelectric-gate field effect transistors (Fe-FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next-generation non-volatile memory. For minimizing gate leakage current of a device which arises from electrically defective ferroelectric polymer layer in particular at low operation voltage, the materials design of interlayers between the ferroelectric insulator and gate electrode is essential. Here, we introduce a new solution-processed interlayer of conductive reduced graphene oxides (rGOs) modified with a conjugated block copolymer, poly(styrene-block-paraphenylene) (PS-b-PPP). A FeFET with a solution-processed p-type oligomeric semiconducting channel and ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) insulator exhibited characteristic source–drain current hysteresis arising from ferroelectric polarization switching of a PVDF-TrFE insulator. Our PS-b-PPP modified rGOs (PMrGOs) with conductive moieties embedded in insulating polymer matrix not only significantly reduced the gate leakage current but also efficiently lowered operation voltage of the device. In consequence, the device showed large memory gate voltage window and high ON/OFF source–drain current ratio with excellent data retention and read/write cycle endurance. Furthermore, our PMrGOs interlayers were successfully employed to FeFETs fabricated on mechanically flexible substrates with promising non-volatile memory performance under repetitive bending deformation.     

An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET

In the present paper, a comprehensive drain current model incorporating various effects such as drain-induced barrier lowering (DIBL), channel length modulation and impact ionization has been developed for graded channel cylindrical/surrounding gate MOSFET (GC CGT/SGT) and the expressions for transconductance and drain conductance have been obtained. It is shown that GC design leads to drain current enhancement, reduced output conductance and improved breakdown voltage. The effectiveness of GC design was examined by comparing uniformly doped (UD) devices with GC devices of various L₁/L₂ ratios and doping concentrations and it was found that GC devices offer superior characteristics as compared to the UD devices. The results so obtained have been compared with those obtained from 3D device simulator ATLAS and are found to be in good agreement.     

Characteristics of metal/tunnel-oxide/n/p+ silicon switching devices—II: Two-dimensional effects in oxide-isolated structures

Effects of oxide isolation on the two-terminal D.C. characteristics of metal/tunnel-oxide/n/p⁺ silicon switching devices have been studied.Recent experimental results have shown that the switching characteristics are strongly dependent on area, and area-to-perimeter ratio of the device. To carry out a systematic investigation of this phenomenon, the devices in this study were isolated using V-grooves of various areas. For a given tunnel-oxide thickness and area, it was found that the magnitude of the switching voltage and holding current of the device increased with isolation area, whereas the switching current remained essentially constant. Furthermore, it is shown that the switching current is almost completely determined by the characteristics of the tunnel-oxide; in particular, the minority carrier concentration at the SiSiO₂ interface. Physical arguments are presented which adequately explain the observed trends. It is also experimentally shown that both switching current and holding current decrease as the tunnel-oxide thickness is increased.A simple two-dimensional model for the oxide-isolated MISS device is derived which effectively explains the above area-related phenomena. In agreement with experimental results, the model predicts that for a given tunnel-oxide thickness and area, an increase in switching voltage magnitude and holding current will result as the isolated p⁺-n junction area is increased. Calculations based on this model are shown to be in good agreement with experimental data.     

A large-signal equivalent circuit model for substrate-induceddrain-lag phenomena in HJFETs

A large-signal HJFET model is developed for drain-lag phenomena caused by deep traps beneath the channel. The model is based on the self-backgating and Shockley-Read-Hall (SRH) statistics. It is shown by two-dimensional (2D) device simulation that electron capture in deep traps is much faster than electron emission under large-signal conditions; therefore, drain current exhibits different responses for rising and falling steps of applied voltage. In the circuit model, electron capture and emission in deep traps are expressed by a parallel circuit consisting of a diode and a resistor, which are physically deduced from SRH statistics. The model agrees well with the 2D simulation results and experimental current-transient data for large-signal voltage steps. In addition, this model accurately describes small-signal drain-conductance dispersion and temperature effects on the trapping phenomena     

Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions

In this paper, we have introduced an analytical subthreshold and strong inversion 3D potential model for rectangular gate (RecG) gate-all-around (GAA) MOSFET. The subthreshold and strong inversion potential distribution in channel region of a RecG MOSFET is obtained respectively by solving 3D Laplace and 3D Poisson equations. The assumed parabolic potential distribution along the z-axis in channel direction is appropriately matched with 3D device simulator after consideration of z-depended characteristic length in subthreshold region. For accurate estimation of short channel effects (SCE), the electrostatics near source and drain is corrected. The precise gate-to-gate potential distribution is obtained after consideration of higher order term in assumed parabolic potential profile. The model compares well with numerical data obtained from the 3D ATLAS as a device simulator and deckbuild as an interactive runtime of Silvaco Inc.     

Facile modification of Cu source–drain (S/D) electrodes for high-performance,low-voltage n-channel organic thin film transistors (OTFTs) based on C60

Exploring suitable electrode materials with sufficiently low work function, ambient stability and low-cost is of great technological importance to the development of n-channel OTFTs. Here, we show that the work function of Cu can be effectively reduced from 4.65 eV to 4.28 eV through surface modification via simply spin-coating a thin layer of branched polyethylenimine (PEI). By exploiting a high-capacitance density gate dielectric (200 nF/cm²), low-voltage (3 V) C₆₀ TFTs with electron mobility (μ_e) of 3.2 cm²/V s are demonstrated with PEI modified Cu as source–drain (S/D) electrodes. In contrast, the device with Cu S/D electrodes possesses μ_e of only 1.0 cm²/V s. The improvement in electrical performance of the PEI modified device is attributed to the efficient electron injection at the Cu/C₆₀ interface which resulted from the reduction in work function of Cu. Moreover, upon PEI modification, the bias stability of the device can be obviously enhanced as compared to the unmodified one, and the resultant device exhibits an excellent thermal stability up to 200 °C without appreciable degradation in mobility. The facile modification of low-cost Cu as S/D electrodes for high-performance n-channel OTFTs as well as the low-voltage operation will pave the way for large scale manufacturing of organic electronics.     

Organic memristive devices based on silver nanoparticles and DNA

A novel organic memory device ‘Al/silver nanoparticles-deoxyribonucleic acid-cetyltrimethylammonium Bromide/ITO’ (Al/Ag NPs–DNA–CTMA/ITO) was fabricated. The measured I–V curve of the device exhibits unipolar switching. The conductivity and the memristive characteristics are significantly improved by the introduction of Ag nanoparticles, but with a poor stability. Better stability is achieved by annealing the device, which also changes the switching characteristic from unipolar to bipolar. As the annealing temperature is raised, the switching voltage first decreases and then increases, while the current I_RESET first increases and then decreases. The range of the optimal annealing temperature is from 383 K to 403 K and the maximum ON/OFF current ratio (I_ON/I_OFF) can reach 10⁴. The switching voltage, the current, and I_ON/I_OFF all increase with the applied voltage amplitude, and V_SET and I_ON/I_OFF obey a quadratic and Boltzmann relationship, respectively.     

Single and dual gate OTFT based robust organic digital design

This paper analyzes and compares the performance of the single gate (SG) and dual gate (DG) organic thin film transistors (OTFTs) based inverter circuits. The DG-OTFT device performs better than SG-OTFT mainly in terms of mobility, on–off current ratio and sub-threshold slope. The mobility of DG device is almost five times higher than the SG, while, an increase of 74% in on–off current ratio and a decrease of 41% in sub-threshold slope are observed. Two different configurations of inverter circuits i.e. diode-load logic (DLL) and zero-V_gs-load logic (ZVLL) are studied. The static and dynamic behaviors of the p-type DLL and ZVLL inverters using SG and DG organic transistors are observed. The DG-OTFT improves gain and noise margins for both DLL and ZVLL inverter circuits. Using DG device, propagation delay reduces by 59% for DLL and 42% for ZVLL as compared to SG OTFT based configurations. Moreover, fixed back gate bias technique further enhances the noise margin and gain by 8% and 18% for DLL and 19% and 26% for ZVLL configurations, respectively. Finally, bootstrapping technique is also applied to the dual gate inverters that further boosts the noise margin and gain for DLL and ZVLL configurations.     

A new analytical subthreshold model of SRG MOSFET with analogue performance investigation

For the first time, a pseudo-two-dimensional (2D) approach is extended from a rectangular device structure to a cylindrical one. A pseudo-2D model applying Gauss's law in the cylindrical channel depletion region for undoped or lightly doped surrounding gate (SRG) silicon metal oxide semiconductor field effect transistor (MOSFETs) working in subthreshold regime is presented. From this pseudo-2D analysis, electrostatic potentials, current characteristics, the threshold voltage roll-off, the drain-induced barrier lowering and the subthreshold swing are explicitly modelled. The obtained analytical model has been extended to develop a model for transconductance-to-drain current ratio (g _m/I _d) in weak inversion regime. Analogue figures of merit of SRG MOSFETs are studied, including transconductance efficiency g _m/I _d, intrinsic gain and output resistance. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modelled expressions are compared with the simulated characteristics obtained from ATLAS device simulator.     

异质栅非对称Halo SOI MOSFET亚阈值电流模型

在沟道源端一侧引入高掺杂Halo结构的异质栅SOI MOSFET,可以有效降低亚阈值电流.通过求解二维泊松方程,为该器件建立了亚阈值条件下的表面势模型.利用常规漂移.扩散理论,在表面势模型的基础上,推导出新结构器件的亚阈值电流模型.为了求解简单,文中给出了一种分段近似方法,从而得到表面势的解析表达式.结果表明,所得到的表面势解析表达式和确切解的结果高度吻合.二维器件数值模拟器ISE验证了通过表面势解析表达式得到的亚阈值电流模型,在亚阈值区二者所得结果吻合得很好.     

一种用于高压电平位移电路结构的准三维模拟方法

A new quasi-three-dimensional （quasi-3D） numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.     

A quasi-3-dimensional simulation method for a high-voltage level-shifting circuit structure

A new quasi-three-dimensional (quasi-3D) numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.     

Two-dimensional subthreshold analysis of sub-micron GaN MESFET

An analytical two-dimensional (2D) model to accurately predict the channel potential and electric field distribution in sub-micron GaN MESFET operating in the sub-threshold regime based on (2D) analytical solution of Poisson's equation using superposition principle is presented. The results so obtained for channel potential, electric field, threshold voltage, etc are compared with simulated data using ATLAS 2D device simulator. The model is then extended to predict the current voltage characteristics and the effects of drain induced barrier lowering (DIBL) on the performance. Furthermore, the sub-threshold output characteristics of the device are also interpreted qualitatively.     

The color change in polychromatic organic light-emitting field-effect transistors: Optical filtering versus reemission

In this contribution the color conversion process of a polychromatic organic light-emitting field-effect transistor (OLET) is revisited on the basis of an analytic device model. The device of interest consists of a color conversion layer out of rubrene on top of a monochromatic light-emitting transistor based on poly(9,9-di-n-octyl-fluorene-alt-benzothiadiazole) (F8BT). The model describes the relation of color coordinate and emission intensity – set by the applied drain and gate biases – linking the optoelectronic response of the employed monochromatic OLET to the optical processes occurring in the color conversion layer. The model shows that the color shift is rather due to partial absorption of the F8BT emission by rubrene than, as was claimed earlier, due to a color conversion process by absorption and reemission in the conversion layer. In addition to the earlier publication, it will be demonstrated that such a device allows for an independent electrical tunability of emission intensity and color coordinate within the color span of the F8BT and the rubrene spectrum being a unique feature of such a polychromatic light-emitting field-effect transistor.     

Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET

In this paper, for the first time, we have analyzed DC characteristics and analog/RF performances for nanowire quadruple-gate (QuaG) gate-all-around (GAA) metal oxide semiconductor field effect transistor (MOSFET), using isomorphic polynomial function for potential distribution. The QuaG GAA MOSFET not only suppresses the short channel effects (SCEs) and offer ideal subthreshold slope (SS), but also is a good candidate for analog/RF device due to its high transconductance (g_m) and high cutoff frequency (f_T). Therefore, this work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. For this, the developed model is based on the solution of 3D Laplace and Poisson׳s equations for subthreshold and strong inversion regions respectively. The developed potential model has been used to formulate a new model for total gate, drain and source charge. Further, the expression for different capacitance for investigating RF performance is obtained from the developed model. Finally, the developed device electrostatics for QuaG GAA MOSFET have been used for the analysis of analog/RF performance. Different capacitances and analog/RF figures of merit are extracted from small signal frequency (1 MHz) ac device simulation. Whereas technology computer-aided design (TCAD) simulations have been performed by 3D ATLAS, Silvaco International.     

Inkjet printed micropump actuator based on piezoelectric polymers: Device performance and morphology studies

All inkjet printed piezoelectric actuators based on poly(vinylidene fluoride-co-trifluoroethylene) (P(VDF–TrFE)) for applications as pump actuators in microfluidic lab-on-a-chip systems (LOC) are manufactured and investigated in terms of their morphology and actuator performance. Furthermore, a pump demonstrator with an all-printed P(VDF–TrFE) actuator is characterized here for the first time. The actuators are manufactured in a fully additive and flexible way by successive inkjet printing of a P(VDF–TrFE) film sandwiched between two silver electrodes on a polyethylene terephthalate (PET) substrate. Different from most current micropumps where actuator elements are fabricated separately, no additional joining step is required in the manufacturing approach employed here. Actuator performance is investigated by measurements of piezoelectric d₃₁ coefficients as well as remanent polarization P_rem for different thermal treatments of the as-printed P(VDF–TrFE) films. A strong dependence of the device performance on the annealing temperature is found with maximum values for d₃₁ and P_rem of approximately 10 pm V⁻¹ and 5.8 μC cm⁻², respectively. Morphology investigations of the printed films by differential scanning calorimetry (DSC), X-ray diffraction (XRD) and Atomic Force Microscopy (AFM) indicate an increased degree of crystallinity of the piezoelectric β-phase for samples annealed at temperatures above 110 °C, which coincides with improved device performance. A basic pumping function with pump rates of up to 130 μL min⁻¹ is demonstrated, which is promising for future applications in LOC. Furthermore, the process chain and characterization presented here can be employed to design and manufacture also other P(VDF–TrFE)-based devices and allows the combination with additional printed on-chip functionalities in future LOC.     

Cooperative MIMO precoding for the LTE-A D2D communications

In the current deployed 4G long term evolution-advanced (LTE-A) system, it adopts the precoding matrix to reduce the effect of the channel fading and improve the system capacity. Besides, a new technique of the device to device (D2D) communication enables the mobile devices using the LTE radio spectrum directly to communicate with each other. In this paper, two precoding selection methods are proposed for the multiple input multiple output (MIMO) D2D communications. The proposed methods adopt the subset and iterative concept to complete the precoding selection. Besides, a resource selection method is also provided for the D2D transmitter to select an appropriate spectrum resource among the nearby users served by the base station. Combined the resource selection with the proposed D2D precoding selection methods, both simulations and experiments demonstrate the excellent performance of the proposed methods.     

An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering

An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model.     

Analytical modeling and parameter extraction of top and bottom contact structures of organic thin film transistors

This paper proposes a structure based model of an organic thin film transistor (OTFT) and analyzes its device physics. The analytical model is developed for the top contact structure by mapping the overlap region to the resistance (in the vertical direction) that includes the contact and the bulk sheet resistances. Total device resistance includes the vertical resistance per unit area of the contact region and the sheet resistance of the channel. In addition, the drain and the gate voltages take into account the potential drop across the respective contacts. The gate bias dependent mobility is considered in place of constant mobility, since; it is more realistic and relevant to the organic TFTs. The proposed analytical model is also applied to the bottom contact structure and the current–voltage (I–V) characteristics are obtained. Furthermore, a differential method is employed to extract the parameters, such as, mobility enhancement factor γ, threshold voltage V_T, mobility µ_B, characteristic length L_C, vertical resistance R_V and contact resistance R_C. Finally, the model is validated in terms of electrical characteristics and performance parameters for both top and bottom contact structures. The analytical model results are in close agreement with the experimental results.