Low gate interface traps AlGaN/GaN HEMTs using a lattice matched ZrZnO transparent gate design

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using a radio-frequency magnetron sputtered ZrZnO transparent oxide layer as a gate insulator are investigated and compared with traditional GaN HEMTs. A negligible hysteresis voltage shift in the C–V curves is seen, from 0.09 V to 0.36 V, as the thickness of ZrZnO films increases. The composition of ZrZnO at different annealing temperatures is observed using X-ray photoelectron spectroscopy (XPS). The ZrZnO thin film achieves good thermal stability after 600 °C, 700 °C and 800 °C post-deposition annealing (PDA) because of its high binding energy. Based on the interface trap density analysis, D_it has a value of 2.663 × 10¹² cm⁻²/eV for 10-nm-thick ZrZnO-gate HEMTs and demonstrates better interlayer characteristics, which results in a better slopes for the I_ds degradation (5.75 × 10⁻¹ mA/mm K⁻¹) for operation from 77 K to 300 K. The 10-nm-thick ZrZnO-gate device also exhibits a flat and a stable 1/f noise, as V_GS–V_th, and at various operating temperatures. Therefore, ZrZnO has good potential for use as the transparent film for a gate insulator that improves the GaN-based FET threshold voltage and improves the number of surface defects at various operating temperatures.     

Thin titanium oxide films deposited by e-beam evaporation with additional rapid thermal oxidation and annealing for ISFET applications

Titanium oxide (TiO₂) has been extensively applied in the medical area due to its proved biocompatibility with human cells [1]. This work presents the characterization of titanium oxide thin films as a potential dielectric to be applied in ion sensitive field-effect transistors. The films were obtained by rapid thermal oxidation and annealing (at 300, 600, 960 and 1200 °C) of thin titanium films of different thicknesses (5 nm, 10 nm and 20 nm) deposited by e-beam evaporation on silicon wafers. These films were analyzed as-deposited and after annealing in forming gas for 25 min by Ellipsometry, Fourier Transform Infrared Spectroscopy (FTIR), Raman Spectroscopy (RAMAN), Atomic Force Microscopy (AFM), Rutherford Backscattering Spectroscopy (RBS) and Ti-K edge X-ray Absorption Near Edge Structure (XANES). Thin film thickness, roughness, surface grain sizes, refractive indexes and oxygen concentration depend on the oxidation and annealing temperature. Structural characterization showed mainly presence of the crystalline rutile phase, however, other oxides such Ti₂O₃, an interfacial SiO₂ layer between the dielectric and the substrate and the anatase crystalline phase of TiO₂ films were also identified. Electrical characteristics were obtained by means of I-V and C-V measured curves of Al/Si/TiO_x/Al capacitors. These curves showed that the films had high dielectric constants between 12 and 33, interface charge density of about 10¹⁰/cm² and leakage current density between 1 and 10⁻⁴ A/cm². Field-effect transistors were fabricated in order to analyze I_D x V_DS and log I_D × Bias curves. Early voltage value of −1629 V, R_OUT value of 215 MΩ and slope of 100 mV/dec were determined for the 20 nm TiO_x film thermally treated at 960 °C.     

Effects of annealing schedule on orientations of Bi3.2Nd0.8Ti3O12 ferroelectric films prepared by metalorganic solution deposition

Fatigue-free Bi_3.2Nd_0.8Ti₃O₁₂ ferroelectric thin films were successfully prepared on p-Si(1 1 1) substrate using metalorganic solution deposition process. The orientation and formation of thin film under different annealing schedules were studied using XRD and AFM. XRD analysis indicated that (2 0 0)-oriented films with degree of orientation of I₍₂₀₀₎/I₍₁₁₇₎ = 2.097 and 0.466 were obtained by preannealing the film at 400 °C for 10 min followed by rapid thermal annealing at 700 °C for 3 min, 10 min and 20 min, respectively, (0 0 8)-oriented film with degree of orientation of I₍₀₀₈₎/I₍₁₁₇₎ = 1.706 were obtained by rapid thermal annealing the film at 700 °C for 3 min without preannealing, and (0 0 8)-oriented film with degree of orientation of I₍₀₀₈₎/I₍₁₁₇₎ = 0.719 were obtained by preheating the film from room temperature to 700 °C at 20 °C/min followed by annealing for 10 min. The a-axis and c-axis orientation decreased as increase in annealing time due to effects of (1 1 1)-oriented substrate. AFM analysis further indicated that preannealing at 400 °C for 10 min followed by rapid thermal annealing at 700 °C for 3 min resulted in formation of platelike crystallite parallel to substrate surface, however rapid thermal annealing at 700 °C for 3 min without preannealing resulted in columnar crystallite perpendicular to substrate surface.     

Annealing temperature effect on electrical and structural properties of Cu/Au Schottky contacts to n-type GaN

Schottky contacts were fabricated on n-type GaN using a Cu/Au metallization scheme, and the electrical and structural properties have been investigated as a function of annealing temperature by current-voltage (I-V), capacitance-voltage (C-V), Auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The extracted Schottky barrier height of the as-deposited contact was found to be 0.69 eV (I-V) and 0.77 eV (C-V), respectively. However, the Schottky barrier height of the Cu/Au contact slightly increases to 0.77 eV (I-V) and 1.18 eV (C-V) when the contact was annealed at 300 °C for 1 min. It is shown that the Schottky barrier height decreases to 0.73 eV (I-V) and 0.99 eV (C-V), 0.56 eV (I-V) and 0.87 eV (C-V) after annealing at 400 °C and 500 °C for 1 min in N₂ atmosphere. Norde method was also used to extract the barrier height of Cu/Au contacts and the values are 0.69 eV for the as-deposited, 0.76 eV at 300 °C, 0.71 eV at 400 °C and 0.56 eV at 500 °C which are in good agreement with those obtained by the I-V method. Based on Auger electron spectroscopy and X-ray diffraction results, the formation of nitride phases at the Cu/Au/n-GaN interface could be the reason for the degradation of Schottky barrier height upon annealing at 500 °C.     

Thermally annealed Ni/n-GaAs(Si)/In Schottky barrier diodes

We have identically prepared as many as eight Ni/n-GaAs/In Schottky barrier diodes (SBDs) using an n-type GaAs substrate with a doping density of about 7.3 × 10¹⁵ cm⁻³. The thermal stability of the Ni/n-GaAs/In Schottky diodes has been investigated by means of current-voltage (I-V) techniques after annealed for 1 min in N₂ atmosphere from 200 to 700 °C. For Ni/n-GaAs/In SBDs, the Schottky barrier height Φ_b and ideality factor n values range from 0.853 ± 0.012 eV and 1.061 ± 0.007 (for as-deposited sample) to 0.785 ± 0.002 eV and 1.209 ± 0.005 (for 600 °C annealing). The ideality factor values remained about unchanged up to 400 °C annealing. The I-V characteristics of the devices deteriorated at 700 °C annealing.     

Effect of rapid thermal annealing on deep level defects in the Si-doped GaN

Rapid thermal annealing effects on deep level defects in the n-type GaN layer grown by metalorganic chemical vapor deposition (MOCVD) have been characterized using deep level transient spectroscopy (DLTS) technique. The samples were first characterized by current-voltage (I-V) and capacitance-voltage (C-V) measurements. The measurements showed that the barrier height of the as-grown sample to be 0.74 eV (I-V) and 0.95 eV (C-V) respectively. However, the Schottky barrier height of the sample annealed at 800 °C increased to 0.84 eV (I-V) and 0.99 eV (C-V) respectively in nitrogen atmosphere for 1 min. Further, it was observed that the Schottky barrier height slightly decreased after annealing at 900 °C. DLTS results showed that the two deep levels are identified in as-grown sample (E1 and E3), which have activation energies of 0.19 ± 0.01 eV and 0.80 ± 0.01 eV with capture cross-sections 2.06 × 10⁻¹⁷ cm² and 7.68 × 10⁻¹⁸ cm², which can be related to point defects. After annealing at 700 °C, the appearance of one new peak (E2) at activation energy of 0.49 ± 0.02 eV with capture-cross section σ_n = 5.43 × 10⁻¹⁷ cm², suggest that E2 level is most probably associated with the nitrogen antisites. Thermal annealing at 800 °C caused the E1 and E3 levels to be annealed out, which suggest that they are most probably associated with the point defects. After annealing at 900 °C the same (E1 and E3) deep levels are identified, which were identified in as-grown n-GaN layer.     

A novel thermally-stable zirconium amidinate ALD precursor for ZrO2 thin films

ZrO₂ thin films were deposited by the atomic layer deposition process on Si substrates using tetrakis(N,N′-dimethylacetamidinate) zirconium (Zr-AMD) as a Zr precursor and H₂O as an oxidizing agent. Tetrakis (ethylmethylamino) zirconium (TEMA-Zr) was also evaluated for a comparative study. Physical properties of ALD-derived ZrO₂ thin films were studied using ellipsometry, grazing incidence XRD (GI-XRD), high resolution TEM (HRTEM), and atomic force microscopy (AFM). The ZrO₂ deposited using Zr-AMD showed a better thermal stability at high substrate temperature (>300 °C) compared to that using TEMA-Zr. GI-XRD analysis reveals that after 700 °C anneal both ZrO₂ films enter tetragonal phase. The electrical properties of N₂-annealed ZrO₂ film using Zr-AMD exhibit an EOT of 1.2 nm with leakage current density as low as 2 × 10⁻³ A/cm² (@V_fb−1 V). The new Zr amidinate is a promising ALD precursor for high-k dielectric applications.     

Characterization of polycrystalline 3C-SiC thin film diodes for extreme environment applications

This paper describes the fabrication and characteristics of polycrystalline (poly) 3C-SiC thin film diodes for extreme environment applications, in which the poly 3C-SiC thin film was deposited onto oxidized Si wafers by APCVD using HMDS as a precursor. In this work, the optimized growth temperature and HMDS flow rate were 1100 °C and 8 sccm, respectively. A Schottky diode with a Au, Al/poly 3C-SiC/SiO₂/Si(n-type) structure was fabricated and its threshold voltage (V_d), breakdown voltage, thickness of depletion layer, and doping concentration (N_D) values were measured as 0.84 V, over 140 V, 61 nm, and 2.7 × 10¹⁹ cm³, respectively. To produce good ohmic contact, Al/3C-SiC were annealed at 300, 400, and 500 °C for 30 min under a vacuum of 5.0 × 10⁻⁶ Torr. The obtained p-n junction diode fabricated by poly 3C-SiC had similar characteristics to a single 3C-SiC p-n junction diode.     

Electrical properties of vacuum annealed La2O3 thin films grown by E-beam evaporation

In this article, the conduction mechanisms of metal-oxide-semiconductor with vacuum annealed Lanthana (La₂O₃) oxide film are investigated. Lanthana films with thicknesses of 3.5, 4.7, and 11 nm were deposited by E-beam evaporation on n-Si (100), and annealed at various temperatures (300-500 °C) in ultra-high vacuum (10⁻¹⁰-10⁻⁹ Torr) for 90 min. From the measurement of spectroscopic ellipsometry, it is found that film thickness is increased with annealing temperature, which would be cause of flat-band voltage shift (ΔV_FB) due to the growth of interfacial layer. From the capacitance measurement, it is found that ΔV_FB of the film is reduced by post-deposition anneal (PDA) compared to that of as-deposited film, but increase again at high temperature annealing, especially in the case of thin film (3.5 nm). From the applied voltage and temperature dependence of the leakage current of the film, with different gate electrode materials (Ag, Al, and Pt), it is shown that the leakage currents are associated with ohmic and Poole-Frenkel (P-F) conductions when flat-band voltage (V_FB) is less than zero, and ohmic and Space-Charge-Limited Current (SCLC) conductions when V_FB is greater than zero. The dielectric constants obtained from P-F conduction for Al gate electrode case is found to be 11.6, which is consistent with the C-V result 11.9. Barrier height of trap potential well is found to be 0.24 eV from P-F conduction. Based on SCLC theory, leakage currents of 3.5 and 11 nm films with different PDA temperatures are explained in terms of oxide trap density.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

Electrical and reliability characteristics of GaAs MOSHEMTs utilizing high-k IIIB and IVB oxide layers

In this work, the high-k material of gadolinium oxide layer (Gd₂O₃) and zirconium oxide layer (ZrO₂) thin films were fabricated as the gate dielectric insulator materials in GaAs metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs). The dielectric constant of Gd₂O₃ and ZrO₂ oxide layers were estimated to be 10.6 and 7.3 by the MOS-ring capacitor of C-V measurements. In addition, the thermal stability of the devices have been investigated and compared with the high-k material Gd₂O₃ and ZrO₂ thin films for reliability tests. The Gd₂O₃ MOSHEMTs achieved a better thermally stable characteristic duo to its similar lattice structure with GaAs native oxide layer. At high temperature operation, the V_BR degradation slope was 1.2 × 10⁻³ V/°C and the maximum I_ds degradation slope was 1.4 × 10⁻² mA (%)/°C. According to this, the device also showed a good reliability characteristic within 48 h. Based on measurement results, the Gd₂O₃ MOSHEMTs exhibited the best electrical characteristics, including the lowest gate leakage current, the lowest noise spectra density, and the high power performance. Therefore, the Gd₂O₃ MOSHEMTs is suitable for high power amplifier and monolithic microwave integrated circuits (MMICs) applications.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.     

The microwave properties of Li doped 0.7(Ba,Sr)TiO3-0.3MgO thick film interdigital capacitors on the alumina substrates

The crystalline and electrical properties of Li doped 0.7(Ba,Sr)TiO₃-0.3MgO thick film interdigital capacitors have been investigated. Screen printing method was employed to fabricate Li doped 0.7(Ba,Sr)TiO₃-0.3MgO thick films on the alumina substrates. (Ba,Sr)TiO₃ materials have high dielectric permittivity (>500 @ 1 MHz) and low loss tangent (0.01 @ 1 MHz) in the epitaxial thin film form. To improve dielectric properties and reduce sintering temperature, MgO and Li were added, respectively. 10 μm thick films were screen printed on the alumina substrates and then interdigital capacitors with seven fingers of 200 μm finger gap were patterned with Ag electrode. Current-voltage characteristics were analyzed with elevated temperature range. Up to 50 °C, the thick films showed positive temperature coefficient of resistivity (dρ/dT) of 6.11 × 10⁸ Ω cm/°C, then film showed negative temperature coefficient of resistivity (dρ/dT) of −1.74 × 10⁸ Ω cm/°C. From the microwave measurement, the relative dielectric permittivity of Li doped 0.7(Ba,Sr)TiO₃-0.3MgO thick films interdigital capacitors were between 313 at 1 GHz and 265 at 7 GHz.     

Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires

In this paper, we report the fabrication and the electrical characterization of Vertical Gate All Around Field-Effect Transistors (GAA-FET) using nonintentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapour Deposition (CVD) using the Vapour-Liquid-Solid (VLS) mechanism as conduction channel. The SiNWs GAA-FET devices exhibited n-channel type semiconductor behaviour whereas the as-grown SiNW FET present p-type behaviour. This effect may be due to positive fixed charge located in the oxide shell or at the Si/SiO₂ interface. Moreover we show that the threshold voltage at room temperature is around −0.95 V, a high I_ON/I_OFF ratio up to 10⁶ with a low I_OFF current about 1 pA, a maximum transconductance (g_m,max ∼ 0.9 μS at V_GS = −0.65 V and V_DS = 1 V) and a minimum inverse subthreshold slope around 145 mV/decade. In light of these characteristics, these devices can be suitable for high performance, low power consumption components and especially for high density integration in integrated circuits (ICs) interconnections regarding to their 3D architecture.     

Temperature dependent current-voltage characteristics of n-MgxZn1−xO/p-GaN junction diodes

This study investigates the temperature dependence of the current-voltage (I-V) characteristics of n-Mg_xZn_1−xO/p-GaN junction diodes. The n-Mg_xZn_1−xO films were deposited on p-GaN using a radio-frequency (rf) magnetron sputtering system followed by annealing at 500, 600, 700, and 800 °C in nitrogen ambient for 60 s, respectively. The n-Mg_xZn_1−xO/p-GaN diode at a substrate temperature of 25 °C had the lowest leakage current in reverse bias. However, the leakage current of the diodes increased with an increase in annealing temperatures. The temperature sensitivity coefficients of the I-V characterizations were obtained at different substrate temperatures (25, 50, 75 100, and 125 °C) providing extracted values of 26.4, 27.2, 17.9, and 0.0 mV/°C in forward bias and 168.8, 143.4, 84.6, and 6.4 mV/°C in reverse bias, respectively. The n-Mg_xZn_1−xO/p-GaN junction diode fabricated with Mg_xZn_1−xO annealed at 800 °C demonstrated the lowest temperature dependence. Based on these findings, the n-Mg_xZn_1−xO/p-GaN junction diode is feasible for GaN-based heterojunction bipolar transistors (HBTs).     

Flexible metal-insulator-metal capacitor using plasma enhanced binary hafnium-zirconium-oxide as gate dielectric layer

We have used a sol-gel spin-coating process to fabricate a new metal-insulator-metal capacitor comprising 10-nm thick binary hafnium-zirconium-oxide (Hf_xZr_1−xO₂) film on a flexible polyimide (PI) substrate. The surface morphology of this Hf_xZr_1−xO₂ film was investigated using atomic force microscopy and scanning electron microscopy, which confirmed that continuous and crack-free film growth had occurred on the PI. After oxygen plasma pre-treatment and subsequent annealing at 250 °C, the film on the PI substrate exhibited a low leakage current density of 3.22 × 10⁻⁸ A/cm² at −10 V and maximum capacitance densities of 10.36 fF/μm² at 10 kHz and 9.42 fF/μm² at 1 MHz. The as-deposited sol-gel film was oxidized when employing oxygen plasma at a relatively low temperature (∼250 °C), thereby enhancing the electrical performance.     

Effect of a silicon nitride buffer layer on the electrical properties of tantalum pentoxide films

Ta₂O₅ films with a buffer layer of silicon nitride of various thicknesses were deposited on Si substrate by reactive sputtering and submitted to annealing at 700 °C in nitrogen atmosphere. The microstructure and the electrical properties of thin films were studied. It was found that with a buffer layer of silicon nitride the electrical properties of Si_xN_y/Ta₂O₅ film can be improved than Ta₂O₅ film. When the thickness of the buffer layer was 3 nm, the Si_xN_y/Ta₂O₅ film has the highest dielectric constant of 27.4 and the lowest leakage current density of 4.61 × 10⁻⁵ A/cm² (at −1 V). For the Si_xN_y (3 nm)/Ta₂O₅ film, the conduction mechanism of leakage current was also analyzed and showed four types of conduction mechanisms at different applied voltages.     

Composition and electrical characteristics of Al2O3-HfO2-HfTiO nanolaminates on Si

A dielectric constant of 27 was demonstrated in the as deposited state of a 5 nm thick, seven layer nanolaminate stack comprising Al₂O₃, HfO₂ and HfTiO. It reduces to an effective dielectric constant (k_eff) of ∼14 due to a ∼0.8 nm interfacial layer. This results in a quantum mechanical effective oxide thickness (EOT) of ∼1.15 nm. After annealing at 950 °C in an oxygen atmosphere k_eff reduces to ∼10 and EOT increases to 1.91 nm. A small leakage current density of about 8 × 10⁻⁷ and 1 × 10⁻⁴ A/cm², respectively at electric field 2 and 5 MV/cm and a breakdown electric field of about 11.5 MV/cm was achieved after annealing at 950 °C.     

Study of ultrathin vanadium nitride as diffusion barrier for copper interconnect

Ultrathin Vanadium nitride (VN) thin film with thickness around 10 nm was studied as diffusion barrier between copper and SiO₂ or Si substrate. The VN film was prepared by reactive ion beam sputtering. X-ray diffraction, Auger electron spectroscopy, scanning electron microscopy and current-voltage (I-V) technique were applied to characterize the diffusion barrier properties for VN in Cu/VN/Si and Cu/VN/SiO₂ structures. The as-deposited VN film was amorphous and could be thermal stable up to 800 °C annealing. Multiple results show that the ultrathin VN film has good diffusion barrier properties for copper.     

Evaluation of graded-channel SOI MOSFET operation at high temperatures

This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold voltage and subthreshold slope were obtained experimentally and by two-dimensional numerical simulations. The results indicated that GC transistors present nearly the same behavior as the conventional SOI MOSFET devices with similar channel length. Experimental analysis of the g_m/I_DS ratio and Early voltage demonstrated that in GC devices the low-frequency open-loop gain is significantly improved in comparison to conventional SOI devices at room and at high-temperature due to the Early voltage increase. The multiplication factor and parasitic bipolar transistor gain obtained by two-dimensional numerical simulations allowed the analysis of the breakdown voltage, which was demonstrated to be improved in the GC as compared to conventional SOI transistors in thin silicon layer devices in the whole temperature range under analysis.