Flicker and thermal noise in an n-channel underlap DG FinFET in a weak inversion region

We propose an analytical model for drain current and inversion charge in the subthreshold region for an underlap DG FinFET by using the minimum channel potential method,i.e.,the virtual source.The flicker and thermal noise spectral density models are also developed using these charge and current models expression.The model is validated with already published experimental results of flicker noise for DG FinFETs.For an ultrathin body,the degradation of effective mobility and variation of the scattering parameter are considered.The effect of device parameters like gate length L_g and underlap length L_un on both flicker and thermal noise spectral densities are also analyzed.Increasing L_g and L_un,increases the effective gate length,which reduces drain current,resulting in decreased flicker and thermal noise density.A decrease of flicker noise is observed for an increase of frequency, which indicates that the device can be used for wide range of frequency applications.     

Analytical modeling of flicker and thermal noise in n-channel DG FinFETs

A compact physics-based thermal and flicker noise model has been developed for n-channel Double Gate FinFETs with varying structural parameters. The effects of mobility degradation due to velocity saturation, carrier heating and channel length modulation have been incorporated for an accurate modeling of noise. The mobility fluctuations dependent on the inversion carrier density have been considered and a characteristic of the flicker noise different from that of Bulk MOSFETs was observed. This has been validated by the experimental results. Based on the proposed thermal and flicker noise model, a compact expression of the corner frequency has been derived and the effects of the structural parameters such as the length and the thickness of the channel have been analyzed. Finally, the model has been applied for p-channel devices and noise behavior in accordance with experimental data has been obtained.     

Impact of leakage current in germanium channel based DMDG TFET using drain-gate underlap technique

In this work, a dual metal (DM) double-gate (DG) Tunnel Field Effect Transistor (DMDG-TFET) with drain-gate underlap is proposed to overcome the challenges in conventional TFET. The ON-current (I_on), OFF-current (I_off), I_on/I_off ratio, subthreshold swing (SS) and ambipolar current (I_ambi) of the proposed device with drain underlap are investigated as gate length is scaled (L_GATE) down. The proposed device gives a better suppression in leakage current and low ambipolar current. The suppressed leakage current (I_off) and ambipolar current (I_ambi) are 9.49 × 10⁻¹⁴ A/µm and 1.95 × 10⁻¹² A/µm respectively for a gate length (L_GATE) of 36 nm and a channel length (L_Ch) of 50 nm for a supply voltage of 0.5 V. Excellent switching behavior is achieved when gate length (L_GATE) is 72% of the channel length (L_Ch). The proposed architecture is suitable for low power applications.     

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DG devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut–off frequency (f_T) and intrinsic voltage gain (A_VO). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate–underlap DG MOSFETs.     

Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs

The impact of the spacer length at the source (L_s) and drain (L_d) on the performance of symmetrical lightly-doped double-gate (DG) MOSFET with gate length L = 20 nm is analyzed, with the type and doping concentration of the spacers kept the same as in the channel material. Using the transport parameters extracted from experimental data of a double-gate FinFET, simulations were performed for optimization of the underlapped gate-source/drain structure. The simulation results show that the subthreshold leakage current is significantly suppressed without sacrificing the on-state current for devices designed with asymmetrical source/drain extension regions, satisfying the relations L_s = L/2 and L_d = L. In independent drive configuration, the top-gate response can be altered by application of a control voltage on the bottom-gate. In devices with asymmetrical source/drain extension regions, simulations demonstrate that the threshold voltage controllability is improved when the drain extension region length is increased.     

Oxide thickness dependent compact model of channel noise for E-mode AlGaN/GaN MOS-HEMT

In this paper, a compact channel noise model for gate recessed enhancement mode GaN based MOS-HEMT which is valid for all regions of operation is proposed. The compact noise model consists of high frequency thermal noise and low frequency flicker noise. The drain current, which is one of the most important parameters for compact noise model is developed by incorporating interface and oxide traps, mobility degradation due to vertical electric field, velocity saturation effect and self-heating effect. The flicker noise model is derived by considering mobility and carrier fluctuation due to traps present in both oxide and interface layer. The thermal noise and flicker noise models are validated by comparing the results with TCAD simulation and experimental results from literature respectively. Effect of thermal and flicker noise power spectral density (PSD) variation with different oxide thickness has also been analyzed.     

Modeling of gate underlap junctionless double gate MOSFET as bio-sensor

In this work, the sensitivity of two types gate underlap Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL DG MOSFET) has been compared when the analytes bind in the underlap region. Gate underlap region considered at source end and drain end once at a time in the channel of JL DG MOSFET. Separate models have been derived for both types of gate underlap JL DG MOSFETs and verified through device simulation TCAD tool sprocess and sdevice. To detect the bio-molecules, Dielectric Modulation technique has been used. The shift in the threshold voltage has been pondered as the sensing parameter to detect the presence of biomolecules when they are bound in gate underlap channel region of the devices.     

An analytical avalanche breakdown model for double gate MOSFET

An analytical model of avalanche breakdown for double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is presented. First of all, the effective mobility (μ_eff) model is defined to replace the constant mobility model. The channel length modulation (CLM) effect is modeled by solving the Poisson’s equation. The avalanche multiplication factor (M) is calculated using the length of saturation region (ΔL). It is shown that the avalanche breakdown characteristics calculated from the analytical model agree well with commercially available 2D numerical simulation results. Based on the results, the reliability of the DG MOSFET can be estimated using the proposed analytical model.     

Performance characteristics of <Emphasis Type="Italic">p</Emphasis>-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

The length of Source/Drain (S/D) extension (L_SDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer L_SDEpFinFET provides a larger series resistance and degrades the drive current (I_DS), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter L_SDE plus the shorter channel length demonstrates a higher trans-conductance (G _m ) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer L_SDE represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current.     

Modeling of noise for p-channel DG-FinFETs

The noise performance of p-channel Double Gate FinFETs has been studied with varying structural parameters. The effects of mobility degradation due to velocity saturation, carrier heating and channel length modulation have been taken into consideration for an accurate modeling of noise. The dependence of mobility fluctuations on the inversion carrier density has been incorporated. This has been validated by the experimental results. The noise behavior of p-channel device has been compared to that of a corresponding n-channel device. It has been observed that noise in p-channel device is comparatively higher due to higher number of oxide-trap density in it. Further, it has been noted that with the same trap density in both p-channel and n-channel device, the flicker noise in the p-channel device is lower than that of the corresponding n-channel device.     

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_0.83In_0.17N and narrowband GaN layers, along with high-k Al₂O₃ as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (V_t), I_on/I_off ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, I_on, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the I_off and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs)

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (V_d). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.     

Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

We propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage V _th, channel length L and gate oxide thickness t _ox are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm technology.     

The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA

The effect of process variations of a FinFET-based low noise amplifier (LNA) are mitigated by using the device in an independently driven mode, i.e. an independently driven double gate (IDDG) FinFET. A 45 nm gate length IDDG FinFET-based cascoded LNA, operating at 5 GHz, is designed and studied to assess the impact of process variation on the LNA performance metrics such as input impedance, gain and noise figure. Four geometrical parameters, gate length, channel width, gate oxide thickness and fin width, and one non-geometrical parameter, channel doping concentration, are considered in the study. The effect of these variations on the input impedance (the desired value is 50 Ω purely real) of the LNA is compensated by the second gate bias of the IDDG FinFET.     

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.     

Analysis of 14nm technology node In0.53Ga0.47As nFinFET integrated with In0.52Al0.48As cap layer for high-speed circuits

CMOS (Complementary Metal-oxide-semiconductor) based high-speed applications in the sub-14 nm technology node using InGaAs Fin field-effect-transistors (FinFETs) confront with inevitable effect in form of interface traps upon integration of dielectric layer with InGaAs material. In this work, we have explored the impact of the traps on short channel effects (SCEs) and a technique of abating the effect of interface traps by introducing In_0.52Al0.₄₈As cap layer. Proposed work reforms the device by varying the cap layer thickness (Tcap), doping concentrations of cap layer and underlap region. The effect of traps on intrinsic delay, work function variation and SCEs was investigated to assess the trend on devices with In_0.52Al_0.48As cap layer. It has been observed that introduction of Tcap improves SCEs and helps to mitigate the effect of interface traps. SCEs can be additionally diminished by presenting underlap fin length at the cost of higher delay. The experimental results show the value of subthreshold swing = 149.54 mV/decade, drain-induced barrier lowering = 38.5 mV V^?1 and delay = 1.1 ps for T_cap = 4 nm without underlap fin length structure for traps concentration of 10¹² cm^?2eV^?1. Thus, significant improvement has been seen in SCEs and delay performance in FinFET structure with cap layer.     

Design Optimization and Performance Projections of Double-Gate FinFETs With Gate–Source/Drain Underlap for SRAM Application

Physical device/circuit simulations are used to explore 6T-SRAM cell design and scaling using double-gate (DG) FinFETs with optimized gate-source/drain (G-S/D) underlap. The underlap is designed for the control of threshold voltage (V_t) in the nanoscale FinFET with undoped ultrathin body (UTB). DG FinFETs with underlap are first characterized in terms of for various S/D-extension lengths (L_ext), lateral doping-density straggles (sigma_L), and fin-UTB thicknesses (w_Si). The relation between and read-static noise margin (SNM) is established to define an optimal SRAM cell, for the Semiconductor Industry Association's International Technology Roadmap for Semiconductors (ITRS) HP45 node with L_g=18 nm, with large SNM as well as large write-0 margin and good immunity to process-induced variations of L_ext, sigma_L, w_Si, and L_g. Then, a scalability study of the DG FinFET-based SRAM cell is done, showing a continual significant benefit of the optimally designed doable underlaps to the end of the ITRS. In addition to the SRAM application, the novel idea of FinFET V_t control via underlap design is stressed, and its application to high-performance CMOS is discussed.     

Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise

The impact of technological processes on Germanium-On-Insulator (GeOI) noise performance is studied. We present an experimental investigation of low-frequency noise (LFN) measurements carried out on (GeOI) PMOS transistors with different process splits. The front gate is composed of a SiO₂/HfO₂ stack with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front and back gate interfaces are characterized and the slow oxide trap densities are extracted. The obtained values are comprised between 5 × 10¹⁷ and 8 × 10¹⁸ cm⁻³eV⁻¹. No correlation between front interface trap density and front interface mobility is observed. We underline a strong correlation between rear interface trap density and rear interface mobility degradation. The impact of Ge film thickness is equally studied. For thin films, the measured drain-current noise spectral density shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by the carrier fluctuation model. The α_H parameter for these devices is 1.2 × 10⁻³. These results are significant for the future development of GeOI technologies.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.