Cascade controller with sliding-mode-voltage and current-mode for monolithic high frequency DC–DC converters

Modern control theories such as fuzzy control, sliding-mode control, optimal control, neural network control have been widely used in discrete-switching DC–DC converters, While they are seldom used in monolithic integration. Under parameter variation, large supply and load disturbance, high slew-rate current transient, high nonlinearity in today and future power management integrated circuits, linear control theories used in traditional monolithic DC–DC converters cannot satisfy required performance, which make it stringent to use modern control theories in monolithic DC–DC converters. This paper proposes cascade controller which consists of PWM based sliding-mode-voltage control and current-mode control for high frequency DC–DC converters. As long as the dynamic responses of the inner current loop are much faster than the outer sliding-mode-voltage loop, inner and outer loops operate in cascade-mode functionally. This work leads to an easy-to-follow design procedure to design control coefficients. To illustrate the feasibility of the scheme, a monolithic 100 MHz boost DC–DC converter using cascade controller with sliding-mode-voltage and current-mode is designed in SMIC 0.18 μm CMOS process. Several simulations are performed to validate the functionalities of the controller.     

Analysis of high voltage step-up nonisolated DC–DC boost converters

A high voltage step-up nonisolated DC–DC converter based on coupled inductors suitable to photovoltaic (PV) systems applications is proposed in this paper. Considering that numerous approaches exist to extend the voltage conversion ratio of DC–DC converters that do not use transformers, a detailed comparison is also presented among the proposed converter and other popular topologies such as the conventional boost converter and the quadratic boost converter. The qualitative analysis of the coupled-inductor-based topology is developed so that a design procedure can be obtained, from which an experimental prototype is implemented to validate the theoretical assumptions.     

Robust feedforward compensation scheme with AC booster for high frequency low voltage buck DC–DC converters

Today and in the future, high frequency low voltage DC–DC converters are an effective power-management solution for fast transient response and small profile in portable electronic systems. This paper presents a robust feedforward compensation scheme with AC booster. An ac amplifier is added in parallel with the main path to compensate the high-frequency gain reduction, which improves gain-bandwidth (GBW) product and slew rate significantly. This approach takes the multistage error amplifier (EA) as an element in the compensation circuit instead of using passive elements used in traditional proportional-plus-integral-and-derivative (PID) compensation circuits. The positive phase shift of left-half-phase (LHP) zeros caused by the feedforward path and ac boosting path in the multistage EA is used to cancel the negative phase shift by the resonant poles of the power stage of buck DC–DC converter in order to compensate the DC–DC converters. A graphical loop-gain method is used to design the feedback compensation and analyze the closed-loop performances of the converter for the complexion arising from the presence of multiple poles of EA before crossover frequency in high frequency converters. The high gain, wide bandwidth, and high slew rate are achieved by the absence of traditional pole-splitting effect and the added ac booster. In addition, the design guidelines for this feedback compensation network realized by robust feedforward with AC booster compensation (RFACBC) scheme and multistage EA are established. When the proposed compensation networks were employed in 100 MHz buck DC–DC converter implemented in SMIC 0.18 μm CMOS process, the simulation results validate the feasibility and functionality of the RFACBC scheme and design guidelines. The closed-loop dc gain achieves over 60 dB with over 20 MHz GBW and 61° phase margin under wide range loads. Furthermore, the settling time is improved due to the advanced frequency compensation.     

Finite-time control of DC–DC buck converters via integral terminal sliding modes

This article presents novel terminal sliding modes for finite-time output tracking control of DC–DC buck converters. Instead of using traditional singular terminal sliding mode, two integral terminal sliding modes are introduced for robust output voltage tracking of uncertain buck converters. Different from traditional sliding mode control (SMC), the proposed controller assures finite convergence time for the tracking error and integral tracking error. Furthermore, the singular problem in traditional terminal SMC is removed from this article. When considering worse modelling, adaptive integral terminal SMC is derived to guarantee finite-time convergence under more relaxed stability conditions. In addition, several experiments show better start-up performance and robustness.     

Trajectory prediction control for digital control DC–DC converters with fast transient response

A novel trajectory prediction control algorithm for digital control DC–DC converters has been presented in this paper. The proposed trajectory prediction control algorithm can provide an accurate prediction of the duty ratio of the next several switching cycles, so as to overcome the inherent time delay of the digital control loop, and to improve the transient response of digital control DC–DC converters, including load response, line response and reference tracking response. A digital control buck DC–DC converter was implemented to verify the effectiveness of the proposed prediction control algorithm. The recovery time is about 8 μs and 4 μs respectively, when the load current changes from a full load to a 17% load and the input voltage changing between 5 V to 6 V. The fastest reference tracking speed is about 26.7 μs/V.     

Critical conditions of saddle-node bifurcations in switching DC–DC converters

Although existence of multiple periodic orbits in some DC–DC converters have been known for decades, linking the multiple periodic orbits with the saddle-node bifurcation (SNB) is rarely reported. The SNB occurs in popular DC–DC converters, but it is generally reported as a strange instability. Recently, design-oriented instability critical conditions are of great interest. In this article, average, sampled-data and harmonic balance analyses are applied and they lead to equivalent results. Many new critical conditions are derived. They facilitate future research on the instability associated with multiple periodic orbits, sudden voltage jumps or disappearances of periodic orbits observed in DC–DC converters. The effects of various converter parameters on the instability can be readily seen from the derived critical conditions. New Nyquist-like plots are also proposed to predict or prevent the occurrence of the instability.     

Fast-transient techniques for high-frequency DC–DC converters

A 30 MHz voltage-mode controlled buck converter with fast transient responses is presented. An improved differential difference amplifier (DDA)-based Type-III compensator is proposed to reduce the settling times of the converter during load transients, and to achieve near-optimal transient responses with simple PWM control only. Moreover, a hybrid scheme using a digital linear regulator with automatic transient detection and seamless loop transition is proposed to further improve the transient responses. By monitoring the output voltage of the compensator instead of the output voltage of the converter, the proposed hybrid scheme can reduce undershoot and overshoot effectively with good noise immunity and without interrupting the PWM loop. The converter was fabricated in a 0.13 µm standard CMOS process using 3.3 V devices. With an input voltage of 3.3 V, the measured peak efficiencies at the output voltages of 2.4, 1.8, and 1.2 V are 90.7%, 88%, and 83.6%, respectively. With a load step of 1.25 A and rise and fall times of 2 ns, the measured 1% settling times were 220 and 230 ns, with undershoot and overshoot with PWM control of 72 and 76 mV, respectively. They were further reduced to 36 and 38 mV by using the proposed hybrid scheme, and 1% settling times were also reduced to 125 ns.     

Lossless average inductor current sensor for CMOS integrated DC–DC converters operating at high frequencies

A novel average inductor current sensing circuit integrable in CMOS technologies is presented. It is designed for DC–DC converters using buck, boost, or buck-boost topologies and operating in continuous conduction mode at high switching frequencies. The average inductor current value is used by the DC–DC controllers to increase the light load power conversion efficiency (e.g., selection of the modulation mode, selection of the dynamic width of the transistors). It can also be used to perform the constant current charging phase when charging lithium-ion batteries, or to simply detect overcurrent faults. The proposed average inductor current sensing method is based on the lossless sensing MOSFET principle widely used in monolithic CMOS integrated DC–DC converters for measuring the current flowing through the power switches. It consists of taking a sample of the current flowing through the power switches at a specific point in time during each energizing and de-energizing cycle of the inductor. By controlling precisely the point in time at which this sample is taken, the average inductor current value can be sensed directly. The circuit simulations were done with the Cadence Spectre simulator. The improvements compared to the basic sensing MOSFET principle are a lower power consumption because no high bandwidth amplifier is required, and less noise emission because the sensing MOSFET is no more switched. Additionally, the novel average inductor current sensing circuit overcomes the low bandwidth limitation previously associated with the sensing MOSFET principle, thus enabling it to be used in DC–DC converters operating at switching frequencies up to 10 MHz and above.     

Favorable basic cells for hybrid DC–DC converters

<正>With the surging demands for extremely high current at sub-1 V supply voltage level in high performance computing and autonomous driving, high density power delivery becomes one of the critical limiting factors for system integration. 48 V power bus system is emerging for these high current applications to reduce the IR losses on the power delivery networks. Thus,     

A design methodology for integrated inductor-based DC–DC converters

A design methodology for monolithic integration of inductor based DC–DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 μm CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.     

A brief review of models of DC–DC power electronic converters for analysis of their stability

A brief review of models of DC–DC power electronic converters (PECs) is presented in this paper. It contains the most popular, continuous-time and discrete-time models used for PEC simulation, design, stability analysis and other applications. Both large-signal and small-signal models are considered. Special attention is paid to models that are used in practice for the analysis of the global and local stability of PECs.     

Design of a hiccup mode over-current protection circuit for DC–DC switching converters

In the paper an improvement hiccup mode over-current protection circuit is proposed and successfully applied in a typical current-mode DC–DC switching converter. It greatly reduces the circuit power consumption in prolonged overload conditions and can provide smooth self-recovery once the overload condition is removed. By reducing the switching frequency and over-current threshold value, it further improves the effect of over-current protection. The power consumption and implementation area are minimized by digital control. By simulation and verification with HSPICE, the output average current is only 16.8% of the conventional over-current mode in continuous over-current conditions. The presented circuits can automatically recover with the maximum load (5 A) when the overload is removed.     

Fuzzy control of dc–dc converters based on user friendly design

The aim of this paper is to show how to build a fuzzy controller and its membership functions automatically. In a fuzzy logic controller (FLC), the proposed method allows one easily to construct a set of membership functions, called shrinking-span membership functions (SSMFs). The FLC uses Mamdani-type fuzzy controllers for the defuzzification strategy and inference operators. The FLC hardware implementation is performed on an 8-bit microcontroller. Simulation results and experimental results demonstrate that the converter can be regulated with good performance even when subjected to input disturbance and load variation. The presented approach is generally valid for the design of an FLC, and can be applied to any dc–dc converter topologies.     

Novel bidirectional DC–DC converters based on the three-state switching cell

It is well known that there is an increasing demand for bidirectional DC–DC converters for applications that range from renewable energy sources to electric vehicles. Within this context, this work proposes novel DC–DC converter topologies that use the three-state switching cell (3SSC), whose well-known advantages over conventional existing structures are ability to operate at high current levels, while current sharing is maintained by a high frequency transformer; reduction of cost and dimensions of magnetics; improved distribution of losses, with consequent increase of global efficiency and reduction of cost associated to the need of semiconductors with lower current ratings. Three distinct topologies can be derived from the 3SSC: one DC–DC converter with reversible current characteristic able to operate in the first and second quadrants; one DC–DC converter with reversible voltage characteristic able to operate in the first and third quadrants and one DC–DC converter with reversible current and voltage characteristics able to operate in four quadrants. Only the topology with bidirectional current characteristic is analysed in detail in terms of the operating stages in both nonoverlapping and overlapping modes, while the design procedure of the power stage elements is obtained. In order to validate the theoretical assumptions, an experimental prototype is also implemented, so that relevant issues can be properly discussed.     

High-voltage high-frequency non-isolated DC–DC converters with passive-saving two-phase QSW-ZVS technique

This paper presents a new technique to improve the power efficiency for high-voltage non-isolated DC–DC converters running at high switching frequencies. A passive-saving two-phase quasi-square-wave zero-voltage-switching (PS-TPZVS) cell that consists of an auxiliary inductor and a capacitor sharing between two phases of sub-converters is proposed to realize ZVS operation for all power FETs under different conditions. Compared to the traditional two-phase ZVS topology, the proposed design saves 1 auxiliary inductor and 1 auxiliary capacitor for establishing ZVS of power FETs, and thus reduces both the volume and power losses of the auxiliary circuitry. To verify the performances of the proposed PS-TPZVS cell, a 140-W 4-MHz two-phase QSW-ZVS converter is designed and verified by simulations to achieve peak efficiencies of 97 % with enhancement-mode GaN FETs and 95 % with power MOSFETs. The proposed PS-TPZVS cell can also be applied to various topologies of non-isolated DC–DC converters and extended into a 2 N-phase topology with only N additional branches of the proposed cell.     

Efficient optimization of fully-integrated inductive DC–DC converters comprising tapered inductor layout synthesis and temperature effects

The evolution of computer-aided design tools has extended the capabilities of a designer by pushing the optimality of complex circuits beyond the ad hoc manual implementation. This work presents a framework to co-optimize the circuit and the layout parameters of fully integrated inductive DC–DC converters. The framework comprises expensive optimization that is speeded up by active learning sample selection and evolutionary techniques to acquire an optimal converter. A tapered inductor topology is used to increase the quality of the on-chip inductor and to improve the efficiency of the overall monolithic DC–DC converter. The optimization framework is validated by co-optimizing the design parameters and the tapered inductor layout for a fully-integrated DC–DC boost converter in a 0.13 μm CMOS technology. The power loss in the circuit is reduced with 27 % resulting in a 7 % efficiency improvement, compared to a fully-integrated DC–DC boost converter with a regular inductor topology.     

Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters

In this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultra-low-power logic block to push these limits and to obtain benefits from this technique in small capacitances. Finally, we proposed to use a stepwise driver in the driving of the gate capacitance of power switches in switched-capacitor (SC) DC–DC converters. We designed and manufactured, in a 130 nm process, a SC DC–DC converter and measured a 29% energy reduction in the gate-drive losses of the converter. This accounts for an improvement of 4% (from 69 to 73%) in the overall converter efficiency.

     

Model predictive control of bidirectional isolated DC–DC converter for energy conversion system

Model predictive control (MPC) is a powerful and emerging control algorithm in the field of power converters and energy conversion systems. This paper proposes a model predictive algorithm to control the power flow between the high-voltage and low-voltage DC buses of a bidirectional isolated full-bridge DC–DC converter. The predictive control algorithm utilises the discrete nature of the power converters and predicts the future nature of the system, which are compared with the references to calculate the cost function. The switching state that minimises the cost function is selected for firing the converter in the next sampling time period. The proposed MPC bidirectional DC–DC converter is simulated with MATLAB/Simulink and further verified with a 2.5 kW experimental configuration. Both the simulation and experimental results confirm that the proposed MPC algorithm of the DC–DC converter reduces reactive power by avoiding the phase shift between primary and secondary sides of the high-frequency transformer and allow power transfer with unity power factor. Finally, an efficiency comparison is performed between the MPC and dual-phase-shift-based pulse-width modulation controlled DC–DC converter which ensures the effectiveness of the MPC controller.     

Signal flow graph modelling and analysis of interleaved DC?DC parallel converters

This paper presents a systematic development of a unified signal flow graph model for an interleaved DC–DC parallel converter system operating in continuous current mode. This signal flow graph approach provides a means to translate directly the switching converter to its graphic model, from which the steady-state and dynamic behaviour of the converter can be studied easily. The development of a unified signal flow graph is explained for a three-cell interleaved parallel converter system. Derivation of large-signal, small-signal and steady-state models from a unified signal flow graph is demonstrated by considering a two-cell interleaved converter system operating in complementary activation mode. Converter performance expressions such as steady-state voltage gain, efficiency expressions and small-signal characteristic transfer functions are also derived. A large-signal model was programmed in a TUTSIM simulator, and the large-signal responses against supply and load disturbances were predicted. Signal flow graph analysis results are validated with PSIM simulations. Experimental observations are provided to validate the signal flow graph modelling method. Further, the mathematical models obtained from the signal flow graph modelling are in agreement with those obtained from the state-space averaging technique.     

Voltage–frequency converter for laser welding control

An experimental model of a voltage–frequency converter was realised and utilised for the control of the thermal behaviour by the laser welding of thermoplastic polymer materials. The input signal of 0–10?V comes from a thermal–optical real-time analysing device of the welding process. The output signal of 0–300?Hz is introduced to the input interface of a laser welding equipment, for setting the laser pulse frequency. Operation tests were performed on the laser welding equipment type HL 124P LCU. The pulses have rectangular waveform, with the amplitude of 20?V. The frequency is very stable, with deviations of less than 0.5?Hz. The waveform and the frequency response at the converter output are appropriate.