A Simple Schmitt Trigger Circuit with Grounded Passive Elements and Its Application to Square/Triangular Wave Generator

This paper introduces a new simple Schmitt trigger circuit using a plus-type differential voltage-current conveyor (DVCC+) and only two grounded resistors. The proposed circuit is very simple and enjoys adjustable lower and higher threshold voltages as well as the output saturation levels. The application of the proposed Schmitt trigger circuit to the square/triangular wave generator is also given. Moreover, a current feedback operational amplifier (CFOA)-based square/triangular wave generator is derived from the proposed DVCC+-based circuit. Simulation and experimental results are presented to exhibit the performance of the proposed circuits.     

A random sequence generator based on chaotic circuits

In this paper, a random sequence generator based on chaotic circuits is presented. Fundamental principle and experimental circuit have been carried out in case of Chua's circuit. The statistical results are in good agreement with probability characteristics of random sequence.     

New voltage controlled oscillators using CFOAs

In this paper, some new current feedback operational amplifier (CFOA)-based voltage-controlled oscillators (VCOs) have been introduced. The proposed circuits offer a number of advantageous features over previously known CFOA-based VCOs. The workability of the presented circuits has been demonstrated using AD844 CFOAs and BFW10 FETs.     

New CFOA-based floating immittance emulators

This paper presents four new topologies for emulating floating immittance functions. Each circuit uses two or three current-feedback operational-amplifiers (CFOAs) and three passive elements. The proposed topologies can emulate positive/negative lossless and lossy floating inductances, and positive/negative capacitance, resistance and inductance multipliers in addition to floating frequency-dependent positive and negative resistances. The functionality of the proposed circuits is verified using the Advanced Design System software and the AD844 CFOA. The simulation results are in excellent agreement with the theoretical calculations.     

An ADC BIST with on-chip ramp generator

This work presents built-in self-test (BIST) techniques for the production testing of mixed signal circuits. The special test strategy for the typical mixed-signal component analog-to-digital converter (ADC) is discussed. The traditional test for such mixed-signal components can be completed through a DSP-based mixed-signal tester with an arbitrary waveform generator and a signal digitizer, but such a test is very costly and time consuming. Hence, a BIST strategy based on an on chip ramp generator (OCRG) is proposed in this work for testing ADC. This BIST method has an advantage testing ADC without DAC to overcome area overhead. This BIST method realizes the test controller, test pattern generation and output response analyser at the aspect of the on-chip circuitry. The demonstration of the proposed BIST is given through various simulation results in the last parts of this work.     

A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector

This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) circuit to achieve a shorter reset path. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate at a lower supply voltage and overcome the dead-band issue of the voltage-controlled delay line. An experimental multiphase-output DLL was designed and fabricated using a TSMC 0.35-$mu$m 2P4M CMOS process. The delay-locked loop (DLL) power consumption is 3.4 mW with a 2 V supply and a 100 MHz input. The measured rms and peak-to-peak jitters are 17.575 ps and 145 ps, respectively. In addition, the supply voltage of the experimental multiphase-output DLL can vary from 1.5 V to 2.5 V without causing malfunctions. The active area is 426 $mu$m $times$ 381 $mu$m.      

1kV/800kHz亚纳秒脉冲发生器设计

提出了以雪崩管作为主开关利用Marx线路来产生高重频高压窄脉冲的方法。分析了雪崩管电路特性,提出了Marx线路下高重频运行时器件的设计要求及印制电路板( PCB)布线设计建议。研制了一台高重频高压亚纳秒脉冲源发生器装置,该装置结构紧凑,在50Ω负载系统下,能输出幅度为1 kV、重复频率为800 kHz、脉宽为500 ps的脉冲。在常温风冷下,该设备可长时间稳定运行。     

Low Voltage Rail to Rail CMOS Current Feedback Operational Amplifier and its Applications for Analog VLSI

This paper presents a new CMOS current feedback operational amplifier (CFOA) with rail to rail swing capability at all terminals. The circuit operates as a class AB for lower power consumption. Besides operating at low supply voltages of ±1.5 V, the proposed CFOA has a standby current of 200 A. The proposed CFOA circuit is thus a versatile building block for low voltage low power applications. The applications of the CFOA to realize a transconductor/multiplier cell, MOS-C differential integrator, MOS-C bandpass filter and MOS-C oscillator are given. PSpice simulations based on 1.2 m level three parameters obtained from MOSIS are given.     

A simple hyperchaos generator based on impulsive switching

This paper studies a simple hyperchaos generator. The circuit consists of three capacitors, three voltage-controlled current sources, and one state-dependent impulsive switch. The circuit dynamics are described by a normal form equation and a two-dimensional noninvertible return map is derived. The return map is calculated precisely using the exact piecewise solution and hyperchaos generation is guaranteed by two positive Lyapunov exponents of the return map. Using a simple test circuit, a typical hyperchaotic attractor can be verified in the laboratory.     

垂直偏移量任意可调的信号发生器的FPGA实现

基于FPGA和直接数字频率合成（DDS）技术,提出一种以软件方法实现波形信号垂直 偏移量任意可调的信号发生器的设计方案,通过引入除法器、加法器、数据取反 器实现对波形信号的幅度调节和垂直偏移量调节。采用FPGA芯片EP1C12Q240C8实验 验证了该波形信号发生器不需要外加硬件电路就可以实现对输出波形垂直偏移量的任意调节 ,且能灵活改变输出波形信号的幅度、相位和频率。     

A low-cost programmable clock generator for switched-capacitor circuit applications

This paper presents two improved circuit techniques that allow the design of a low-cost programmable clock generator using a ring oscillator for low-frequency switched-capacitor applications. The first technique aims at reducing the frequency of the oscillator with small capacitors by proposing a Miller current-starved inverter ring oscillator. For identical values of integrated components in implementation, the proposed ring oscillator reduces the oscillation frequency by 5 times over the conventional ring oscillator and 3 times over the conventional current-starved inverter ring oscillator. This benefits the relaxation of PSRR requirement and the reduction of substrate noise coupling in mixed-signal circuits. The second technique aims at enhancing the reliability of the programmed data by proposing orthogonal fusible link trimming circuit. The experimental results have verified that the programming range of 56 kHz to 1.042 MHz is achieved using discrete-step tuning on small capacitor values from 0.375 pF to 5.625 pF together with frequency division by four divider stages, whilst the jitter is less than 300 ps at ±10% variation in a 5 V supply in the entire tuning range. Wing Foon Lee was born in Singapore. He had worked as an application engineer for more than two years. He received his B.Eng., M.Eng. and Ph.D. degrees in Electrical & Electronic Engineering from Nanyang Technological University, Singapore in 1996, 1999 and 2005 respectively. His research interest is on low power analog circuit design, high precision readout circuits and signal-conditioning circuits for sensor applications. P. K. Chan was born in Hong Kong. He received the B.Sc. (Hons) degree from the University of Essex, Colchester, U.K., in 1987, the M.Sc. degree from the University of Manchester, Institute of Science and Technology (U.M.I.S.T.), Manchester, U.K., in 1988, and the PhD degree from the University of Plymouth, U.K. in 1992. From 1989 to 1992, he was a Research Assistant with the University of Plymouth, working in the area of MOS continuous-time filters. In 1993, he joined the Institute of Microelectronics (IME) as a Member Technical Staff, where he designed CMOS sensor interfaces for industrial applications. In 1996, He was a Staff Engineer with Motorola, Singapore where he developed the magnetic write channel for Motorola 1st generation hard-disk preamplifier. He joined Nanyang Technological University (NTU), Singapore in 1997, where he is currently an Associate Professor in the School of Electrical and Electronic Engineering and Program Director [analog/mixed-signal IC and applications] for the Center for Integrated Circuits and Systems (CICS). He holds four patents and is an IC Design Consultant to local and multi-national companies in Singapore. He has also conducted numerous IC design short courses to the industrial companies and design centers. His research interests include circuit theory, amplifier frequency compensation techniques, sensing interfaces for integrated sensors, biomedical circuits and systems, integrated filters and data converters.     

Design of Z-copy controlled-gain voltage differencing current conveyor based adjustable functional generator

This paper introduces interesting active element and its application in the field of square and triangular wave generators. Active element, so-called Z-Copy Controlled Gain Voltage Differencing Current Conveyor (ZC-CG-VDCC), has availability of three mutually independently and electronically adjustable parameters (transconductance, intrinsic resistance of the current input terminal and current gain between two terminals) that are very popular for control of applications today. In addition, a proposed device utilizes very useful z-copy (additional auxiliary terminal) features and two terminals providing voltage difference. All mentioned features are beneficial in mixed-mode circuit synthesis and design of adjustable applications (active filters, oscillators, generators, modulators, etc.). Electronically adjustable properties of the device are involved in the design of an adjustable generator. The generator provides voltage- and current-mode square wave outputs that can be also used for differential square wave output when very simply modified. Application of the generator in simple pulse width modulator (PWM) is also introduced. A detailed analysis and Spice simulation results are given and main features of the circuits are compared to electronically controllable solutions of recent development in this field.     

Analog built-in saw-tooth generator for ADC histogram test

This paper presents an analog built-in saw-tooth generator to be used for linear histogram test of ADCs. The internal generation of a highly linear signal with precise amplitude control relies on the use of an original calibration scheme. The effectiveness of the calibration procedure is evaluated through simulations and results demonstrate that ramp signals with a linearity of 15 bits and an average slope error of 0.4% can be achieved. In addition, the proposed implementation exhibits a very low silicon area, making the generator suitable for BIST application.     

PLL-based BiCMOS on-chip clock generator for very high-speedmicroprocessor

Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 μm BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz     

New two-CFOA-based floating immittance simulators

This paper presents new topologies for emulating floating immittance functions using three to five passive elements and only two current-feedback operational-amplifiers (CFOAs). The feasibility of using only two CFOAs and two passive components is explored. The proposed topologies can emulate lossy positive and negative inductances and capacitance-, inductance-, resistance-multipliers, and frequency dependent negative and positive conductances. The functionality of the proposed circuits was experimentally verified using the commercially available AD844 CFOA. The experimental results are in excellent agreement with theoretical calculations.     

On the Realization of Universal Current Mode Biquads Using a Single CFOA

The four terminal Current feedback op-amps (CFOA) with an external compensation pin, such as AD844, have received prominent attention during the past decade as alternative building blocks for analog circuit design because of their significant advantages over the traditional voltage-mode op-amp (VOA). A popular application of CFOAs has been in realizing voltage-mode (VM) and current-mode (CM) biquad filters. Previously known universal CM biquads (i.e. those capable of realizing all the five generic filter functions namely, low-pass, band-pass, high-pass, notch and all-pass) realizable with CFOAs require two to nine CFOAs. Although a few dual-function/three-function single-CFOA-based CM circuits have appeared in literature, no single-CFOA-based canonic universal CM biquad with explicit CM output has been reported in the literature up until now. This paper fills this void by presenting a set of eight minimal universal CM biquads all of which are realizable with only a single CFOA. The non-ideal analysis of the proposed circuits has been presented, their comparative features, advantages and limitations have been brought out. The workability of all the proposed circuits has been confirmed by PSPICE simulations and experimental results based upon AD844 type CFOAs.     

New analogue inverse filters realised with current feedback op-amps

This article presents new configurations for realising analogue inverse lowpass, inverse bandpass, inverse highpass and inverse bandreject filters using commercially available current feedback op-amps (CFOA) with an accessible z-terminal (such as AD844). The workability of the proposed circuits has been confirmed by experimental results by employing AD844-type CFOAs.     

Compact discrete-time chaos generator circuit

A three-transistor CMOS circuit is presented, with adjustable nonlinear characteristics, which can be used as a map that generates discrete-time chaotic signals. A method of constructing a chaos generator using two map circuits is also proposed. The circuit is very compact, which makes it suitable for applications requiring the integration of a large number of random signal generators on a single VLSI chip.     

Logistic chaotic sequence generator based on physical unclonable function

Logistic nonlinear chaotic system has many good characters such as initial value sensitivity and topological mixing in the some parameter condition,which is used to create the random sequence signal generator.Because of the attributions of randomness and uniqueness even under the exact,the same circuit layouts and manufacturing procedures,there is still an instinct unclonable difference in each integrated circuit.Therefore,a new sequence stream generator was proposed based on Logistic chaotic system and physical unclonable function designed by double output look-up-table (LUT).The output of the Logistic sequence generator was associated with a specific physical circuit.This kind of sequence generator could resist an attack such as the replication of the keys of the system.The system was designed and tested on the Xilinx FPGA board.The results show that the same architecture of the circuit and the same config file operated on the different FPGA developing board can generate the total different random chaotic sequence stream and improve the randomness of the stream.