Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

A SiGe LC-ladder low noise amplifier with base resistance match,gain and noise flatness for UWB applications

This study presents a 3.1–10.6 GHz ultra-wideband low noise amplifier (UWB LNA) in 0.18 µm SiGe HBT technology. To achieve a good input match, parasitic base resistance in a bipolar transistor and an LC-ladder filter are included into calculations with the common-emitter topology using shunt–shunt capacitive feedback. Both high and flat power gain (S₂₁) and low and flat noise figure (NF) are achieved by adjusting the pole and zero in amplifying stage and quality factors of the fourth-order input network. Design equations for performances such as gain, noise figure and linearity IIP3 are derived especially on gain flatness and noise flatness. LNA dissipates 33 mW power and achieves S₂₁ of 20.65+0.7 dB, NF of 2.79+0.2 dB over the band of 3.1–10.6 GHz. The simulated input third-order intermodulation point (IIP3) is −17 dBm at 10 GHz.     

Record gain at 3.1 GHz of 4H-SiC high power RF MESFET

In this paper, a very high gain 4H-SiC power MESFET with incorporation of L-gate and source field plate (LSFP-MESFET) structures for high power and RF applications is proposed. The influence of L-gate and source field plate structures on saturation current, breakdown voltage (V_b) and small-signal characteristics of the LSFP-MESFET was studied by numerical device simulation. The optimized results showed that V_b of the LSFP-MESFET is 91% larger than that of the 4H-SiC conventional MESFET (C-MESFET), which meanwhile maintains almost 77% higher saturation drain current characteristics. The maximum output power densities of 21.8 and 5.5 W/mm are obtained for the LSFP-MESFET and C-MESFET, respectively, which means about 4 times larger output power for the proposed device. Also, the cut-off frequency (f_T) of 23.1 GHz and the maximum oscillation frequency (f_max) of 85.3 GHz for the 4H-SiC LSFP-MESFET are obtained compared to 9.4 and 36.2 GHz for that of the C-MESFET structure, respectively. The proposed LSFP-MESFET shows a new record maximum stable gain exceeding 22.7 dB at 3.1 GHz, which is 7.6 dB higher than that of the C-MESFET. To the best of our knowledge, this is 2.5 dB greater than the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

A 65 mW, 0.4–2.3 GHz Bandpass Filter for Satellite Receivers

A monolithic tunable bandpass filter for satellite receiver front-ends is presented. The center frequency of the bandpass filter can be tuned from 0.4 GHz to 2.3 GHz. The filter is constructed using four transconductor-C poly-phase filter sections and has a 50 dB variable gain range. At 20 dB attenuation and at 30 dB gain the measured 1 dB compression point is –21 dBm and –56 dBm, respectively. Measured input IP3 is –12 dBm. The noise figure is 15 dB at maximum gain. An on-chip I/Q oscillator tracks the center frequency and enables automatic tuning. The bandpass filter dissipates 65 mW with 5 Volt supply voltage and occupies 0.16 mm² chip area. The filter is realized in a standard 11 GHz f _t bipolar technology.     

5–11 GHz CMOS PA with 158.9 ± 41 ps group delay and low power using current-reused technique

This paper proposes the design of a low group delay and low power ultra-wideband (UWB) power amplifier (PA) in 0.18 μm CMOS technology. The PA design employs two stages cascade with inductive peaking technique to provide broad bandwidth characteristic and higher gain while gain flatness can be achieved by connecting inter-stage circuit. A common gate current-reused technique is adopted at the first stage amplifier to achieve good input matching, low group delay and low power. The simulation results show that the proposed PA design has an average gain of 11.5 dB with flatness of ±0.4 dB from 5–11 GHz, while maintaining bandwidth of 4.2–12.3 GHz. An input return loss (S₁₁) less than −10.4 dB and output return loss (S₂₂) less than −9.5 dB, respectively are obtained. The PA design achieves excellent phase linearity (i.e., group delay variation) of ±41 ps and only consuming 17 mW power from 1.2 V supply voltage. A good output 1-dB compression point OP1 dB of 3.7 dBm is obtained. By using this method, the proposed design has low group delay variation and lowest power among the recently reported UWB CMOS PAs applications.     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

InAs/AlSb HEMTs for cryogenic LNAs at ultra-low power dissipation

Properties of the InAs/AlSb high electron mobility transistor, essential for the design of a cryogenic low-noise amplifier (LNA) operating at low power dissipation, have been studied. Upon cooling from 300 K to 77 K, the dc transconductance g_m was enhanced by 30% at a drain-source voltage V_DS of 0.1 V. The gate current leakage showed a strong reduction of the Schottky current component at 77 K. Compared to 300 K, the cut-off frequency f_T and maximum oscillation frequency f_max showed a significant improvement at 77 K with a peak f_T (f_max) of 167 (142) GHz at V_DS = 0.2 V. The suitability of the Sb HEMT for a cryogenic LNA design up to 50 GHz, operating at low dc power dissipation, was investigated through the extraction of the NF_tot,min figure of merit. It was found that the best device performance in terms of noise and gain is achieved at a low V_DS of 0.16 V resulting in a minimum NF_tot,min of 0.6 dB for a frequency of 10 GHz when operating at 77 K. A benchmarking between the Sb HEMT and an InP HEMT has been conducted highlighting the device improvement in noise and gain required to reach today’s state-of-the-art cryogenic LNAs.     

A low-noise mixer with an image-reject notch filter for 2.4 GHz applications

This paper presents a low noise first down-conversion mixer with a notch filter for the heterodyne receiver. The notch filter connected to the output node of the mixer driver stage plays a role of image rejection at an image frequency, thereby suppressing the sideband image noise and improving the mixer noise performance. Targeted for 2.4 GHz industrial-scientific-medical band applications, a simple source-degenerated down-conversion single balanced mixer with the filter is implemented. The measurement results of the proposed down-conversion mixer shows about 3.0 dB improvement of single-side band noise figure, about 2.9 dB power conversion gain improvement, and 25 dB image suppression compared to those without the filter dissipating 4 mA from a 2.5 V supply voltage.     

Post-linearization with image rejection for high IIP3 and image-rejection ratio of a 17 GHz CMOS low noise amplifier

This study develops a post-linearization technique to simultaneously improve the input third-order intercept point (IIP3) and image-rejection ratio (IRR) of a 17 GHz low noise amplifier (LNA) in a 0.18 μm standard CMOS process. A third-order intermodulation distortion (IMD3) compensator constructed by a second-order notch filter was proposed to achieve both high linearity and image reject (IR) of the cascode LNA. The correlation between the post-linearization and IR techniques is analyzed and discussed. The measured LNA achieved a gain of 16.5 dB, a noise figure (NF) of 4.58 dB, an IIP3 of 0 dBm, and an IRR from 68 to 78 dB. The improvements of IIP3 and IRR are 11.7 and 46 dB, respectively, better than that of the LNA without the notch filter. The proposed IR LNA with total current dissipation of 4.8 mA under 1.8 V supply voltage and notch filter only dissipate a DC power of 2 mW.     

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18 μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6 GHz. The resonance points were set in 3 GHz and 10 GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S₂₁>10 dB) with a good input impedance matching less than –10 dB and a minimum noise figure of 2.9 dB over the entire band. The proposed UWB LNA consumed 15.2 mW from a 1.8 V power supply.     

A flip-chip packaged 80-nm In0.7Ga0.3As MHEMT for millimeter-wave low-noise applications

In this paper, we present a flip-chip 80-nm In_0.7Ga_0.3As MHEMT device on an alumina (Al₂O₃) substrate with very little decay on device RF performance up to 60 GHz. After package, the device exhibited high I_DS = 435 mA/mm at V_DS = 1.5 V, high g_m = 930 mS/mm at V_DS = 1.3 V, the measured gain was 7.5 dB and the minimum noise figure (NF_min) was 2.5 dB at 60 GHz. As compared to the bare chip, the packaged device exhibited very small degradation in performance. The result shows that with proper design of the matching circuits and packaging materials, the flip-chip technology can be used for discrete low noise FET package up to millimeter-wave range.     

Improvement on the noise performance of InAs-based HEMTs with gate sinking technology

Improvement on the RF and noise performance for 80 nm InAs/In_0.7Ga_0.3As high-electron mobility transistor (HEMT) through gate sinking technology is presented. After gate sinking at 250 °C for 3 min, the device exhibited a high transconductance of 1900 mS/mm at a drain bias of 0.5 V with 1066 mA/mm drain-source saturation current. A current-gain cutoff frequency (f_T) of 113 GHz and a maximum oscillation frequency (f_max) of 110 GHz were achieved at extremely low drain bias of 0.1 V. The 0.08 × 40 μm² device with gate sinking demonstrated 0.82 dB minimum noise figure and 14 dB associated gain at 17 GHz with only 1.14 mW DC power consumption. Significant improvement in RF and noise performance was mainly attributed to the reduction of gate-to-channel distance together with the parasitic source resistance through gate sinking technology.     

A low-voltage high-linearity ultra-wideband down-conversion mixer in 0.18-μm CMOS technology

This paper presents a wideband mixer chip covering the frequency range from 3.4 to 6.8 GHz using TSMC 0.18 μm CMOS technology. The linearity can be improved using multiple-gated-transistors (MGTR) topology. The measured 3-dB RF frequency bandwidth is from 3.1 to 6.8 GHz with an IF of 10 MHz. The measured results of the proposed mixer achieve 7.2-4.3 dB power conversion gain and 2-3 dBm input third-order intercept point (IIP3), and the total dc power consumption of this mixer including output buffers is 2.9 mW from a 1 V supply voltage. The current output buffer is about 2.17 mW, and the excellent LO-RF isolation achieved up to 54 dB at 5 GHz. The paper presents a mixer topology that is very suitable for low-power in ultra-wideband system applications.     

Design of a tunable frequency CMOS fully differential fourth-order Chebyshev filter

A new fully differential amplifier and a fully differential R-MOSFET-C fourth-order Chebyshev active lowpass filter employing passive resistors and current-steering MOS transistors as variable resistors are proposed. The implementation relies on the tunability of current-steering MOS transistors operating in the triode region which counteract the deviation of resistors in integrated circuit manufacturing technology in order that the cutoff frequency of Chebyshev active filter can be realized accurately tunable. The amplifier is not only with voltage common-mode negative feedback (VCMFB), but also with current common-mode negative feedback (CCMFB), which will benefit for the stability of its DC operating point. A cutoff frequency of 138 kHz fourth-order Chebyshev lowpass filter was designed and fabricated using 3.3 V power supply and 0.35 μm CMOS technology. Chip test results demonstrate better than −68 dB THD with 70 kHz, 2.0V_pp signal, frequency turning range of more than 14,000 from 3 Hz to 420 kHz, chip area of 0.36 mm² and power consumption of 16 mW.     

Ultra low voltage, high performance operational transconductance amplifier and its application in a tunable Gm-C filter

This paper presents an ultra low voltage, high performance Operational Transconductance Amplifier (OTA) and its application to implement a tunable Gm-C filter. The proposed OTA uses a 0.5 V single supply and consumes 60 μw. Employing special CMFF and CMFB circuits has improved CMRR to 138 dB in DC. Using bulk driven input stage results in higher linearity such that by applying a 500 mv_p-p sine wave input signal at 2 MHz frequency in unity gain closed loop configuration, third harmonic distortion for output voltage is −46 dB and becomes −42.4 dB in open loop state for 820 mv_p-p output voltage at 2 MHz. DC gain of the OTA is 47 dB and its unity gain bandwidth is 17.8 MHz with 20 pF capacitance load due to both deliberately optimized design and special frequency compensation technique. The OTA has been used to realize a wide tunable Gm-C low-pass filter whose cutoff frequency is tunable from 1.4 to 6 MHz. Proposed OTA and filter have been simulated in 0.18 μm TSMC CMOS technology with Hspice. Monte Carlo and temperature dependent simulation results are included to forecast the mismatch and temperature effects after fabrication process.     

RF CMOS active inductor band pass filter with post fabrication calibration

This paper presents an active inductor bandpass filter (BPF) architecture with selectable 50 Ω driving capability and post fabrication calibration for gain, center frequency, and quality factor. The design details, and performance assessment that facilitate selecting an offline calibration mode to measure and tune post fabrication BPF performance are discussed. A specific design example for a L1/L2 channel GPS receiver is included with a BPF that is required to pass the L2 signal centered at 1.227 GHz with a gain of approximately16 dB at the center frequency, have a 3 dB bandwidth of 30 MHz (Q = 41) and rejection of the L1 signal at 1.575 GHz by at least 60 dB relative to the center frequency. A multistage active inductor BPF 90 nm CMOS design is presented that meets these specifications with typical process parameters. It is demonstrated that the post fabrication design based on typical corner analysis can be re-tuned to the desired performance for process variations across the slow and fast corners using the offline measuring and tuning control inputs.     

Design of ultra wideband trapezoidal shape slot antenna with circular polarization

A CPW-feed printed slot antenna with circular polarization characteristics is presented in this paper. The basic structure of the antenna is a rectangular slot excited by a 50 Ω CPW line terminated on a trapezoidal shaped tuning stub. Perturbations in the form of circular stubs are applied in the slot to realize circular polarization. The measured impedance bandwidth (S₁₁ < −10 dB) for the initial design is 4.4 GHz (from 2.2 GHz to 6.6 GHz) while the 3-dB axial ratio bandwidth is 1.77 GHz (from 4 GHz to 5.77 GHz) which is 36.23% at the center frequency of 4.88 GHz. The basic structure of the antenna was further modified to enhance the impedance bandwidth to reach well beyond 12 GHz while increasing the ARBW to 44.3% (from 4.3 GHz to 6.75 GHz). The proposed antenna in its final version has a measured peak gain of about 5 dB throughout the useful band and nearly stable radiation pattern.     

Design of low power UWB LNA based on common source topology with current-reused technique

This paper presents two low power UWB LNAs with common source topology. The power reduction is achieved by the current-reused technique. The gain and noise enhancement of the proposed circuit is based on an output buffer which is used by a common source amplifier with shunt–shunt feedback. Chip1 is an adopted T-match input network of 50 Ω matching in the required band. Measurements show that the S₁₁ and S₂₂ are less than −10 dB, and the maximum amplifier gain S₂₁ gives 9.7 dB, and the noise figure is 4.2 dB, the IIP3 is −8.5 dBm, and the power consumption is 11 mW from 1.1 V supply voltage. The input matching of chip2 is adopted from a LC high pass filter and source degenerated inductor. The output buffer with the RC-feedback topology can improve the gain, increase the IIP3, restrain the noise, improve the noise figure and decrease the DC power dissipation. Measurements show 13.2 dB of power gain, 3.33 dB of noise figure, and the IIP3 is −3.3 dBm. It consumes 9.3 mW from 1.5 V supply voltage. These two chips are implemented in a 0.18 μm TSMC CMOS process.     

Accurate modeling of nanoscale gate underlap SOI MOSFET and design of low noise amplifier for RF applications

Paper presents an accurate model by accounting non-quasi-static and extrinsic parasitic effects for 90 nm gate underlap SOI MOSFETs for RF applications. Generated Y-parameters from the model up to 20 GHz matched very well with 2D ATLAS (with an average error of ～5%), whereas results from quasi-static predictive technology model differ significantly (>20%). Calculated transit frequency f _T and maximum frequency of oscillation f _max have been found as ～108 and ～130 GHz respectively. Simulated noise figure at drain-to-source current I _DS ≈ 0.64mA and drain-to-source voltage V _DS=1 V was found to be ≈2.8 dB with gate resistance R _ge = 3 Ω. A low noise amplifier (LNA) designed at operating frequency of 5.8 GHz using the model has shown good match at input (S ₁₁ ≈ ?15 dB), output (S ₂₂ ≈ ?16 dB) and gain (S ₂₁ ≈ 15 dB). A new figure-of-merit of LNA (FoM_LNA) involving signal power gain G, noise factor F and dc power consumption P _dc has been proposed. By comparing with limited available measured data of 180 nm bulk, it has been found that underlap LNA (simulated using the developed model) gives almost three times improvement in the proposed FoM_LNA.     

A single-chip CMOS IF-band converter design for DVB-T receivers

This paper describes a CMOS single-chip IF-band converter (IFC) which is applied in the analog front end circuitry of DVB-T receivers. The proposed IFC is composed of a down-conversion mixer, an automatic gain controller (AGC), and an anti-aliasing filter (AAF). The down-conversion mixer uses a current folded-mirror technique which converts a 36 MHz intermediate frequency (IF) input into a 4.5 MHz baseband signal. The AGC loop applies a novel digital variable gain amplifier (VGA) basing on a g_m-boosting DVGA (digital VGA). A total of three tunable gain stages are cascaded to provide a 70 dB dynamic range. A temperature-compensated 6th order transconductance-C (Gm-C) filter with digitally tunable bandwidth (6, 7, 8 MHz) is used to constitute the proposed AAF. Moreover, a temperature-compensated circuitry is used to neutralize the AAF's bandwidth drifting caused by the temperature variation.