Current mode charge pulse amplifier in CMOS technology for use withparticle detectors

0This amplifier is intended to be part of the front-end of a larger read-out chip to be used with particle detectors. The demands of read-out electronics are low power, low noise and high speed. At the input a charge pulse of 25000 electrons (4fC) is applied to study the behaviour of the amplifier. The amplifier has a gain of ±12 mV/fC depending on the biasing condition, a peaking time of 35 ns and a power consumption of <500 μW     

High performance low noise charge preamplifier with DC coupling toparticle silicon detectors in CMOS technology

A low noise, low power CMOS charge preamplifier with DC coupling to particle silicon detectors has been designed. Simulation results show that the detector leakage current can be compensated up to 8 μA. The proposed charge amplifier has been simulated and implemented with a CMOS silicon-on-insulator process. A total RMS output noise voltage of 0.58 mV for a detector capacitance of 10 pF and a DC leakage current of 5 μA and a conversion gain of 2.86 mV/fC with 0.66 mW power consumption have been obtained     

An integrated readout circuit for personal dosimetry with phase-shift compensation technique to improve stability

In this paper an integrated CMOS readout circuit for a radiation detector in a personal dosimeter is presented. High counting rate and low power requirements make the stability of the conventional high-pass pulse shaper a big problem. A novel phase-shift compensation method is proposed to improve the phase margin. The principle of the compensation circuit and its influence on noise performance are analyzed theoretically. A readout chip with two channels of conventional structure and one channel of the proposed structure has been implemented in a 0.35 μm CMOS technology. It occupies an area of 2.113×0.81 mm². Measurement results show that the proposed channel can process up to 1 MHz counting rate and provide a conversion gain of about 170 mV/fC at a power dissipation of 330 μW with a 3.3 V power supply. Ac-coupled to a silicon PIN detector, it successfully detects β-rays.     

一种兼顾速度和功率损耗的硅探测器模拟前端电路设计

提出了一种兼顾速度和功率损耗的增益可调模拟前端电路,适用于硅探测器。该电路主要由快速电荷灵敏放大器、整形器以及可调节主要参数的控制系统组成。其中快速电荷灵敏放大器由低噪音场效晶体管（JFET）和电流反馈运算放大器构成,以确保较高频率和较短上升时间。整形器为五阶复数滤波器,能够提供较高的对称脉冲。通过实验验证了其可行性,在电容小于100 pF的范围内,实现了6种可调增益且兼顾了速度和功率损耗,电荷灵敏放大器上升时间为12ns,功率损耗为96mW。当探测器电容为40 pF时,等效噪音电荷（ENC）均值为180e-。     

5–11 GHz CMOS PA with 158.9 ± 41 ps group delay and low power using current-reused technique

This paper proposes the design of a low group delay and low power ultra-wideband (UWB) power amplifier (PA) in 0.18 μm CMOS technology. The PA design employs two stages cascade with inductive peaking technique to provide broad bandwidth characteristic and higher gain while gain flatness can be achieved by connecting inter-stage circuit. A common gate current-reused technique is adopted at the first stage amplifier to achieve good input matching, low group delay and low power. The simulation results show that the proposed PA design has an average gain of 11.5 dB with flatness of ±0.4 dB from 5–11 GHz, while maintaining bandwidth of 4.2–12.3 GHz. An input return loss (S₁₁) less than −10.4 dB and output return loss (S₂₂) less than −9.5 dB, respectively are obtained. The PA design achieves excellent phase linearity (i.e., group delay variation) of ±41 ps and only consuming 17 mW power from 1.2 V supply voltage. A good output 1-dB compression point OP1 dB of 3.7 dBm is obtained. By using this method, the proposed design has low group delay variation and lowest power among the recently reported UWB CMOS PAs applications.     

A low-power high-gain transresistance BiCMOS pulse amplifier forcapacitive detector readout

A low-power, high-gain amplifier for detector readout is discussed. The amplifier is balanced, fully differential in circuit topology, and symmetrical in layout, making it radiation tolerant and relatively insensitive to varying magnetic fields in the large detector. Before irradiation, the circuit has a measured differential gain of 110 mV/4 fC, an average 10/90% rise time t_10/90% of 19 ns, a noise figure of 433⊕93·(C_t)^1.08 electrons, e^-, and a power consumption of 750 μW. To keep the core amplifier stable, a low-power super-low gain-bandwidth (SL-GBW) amplifier with a small area is used and also discussed. The SL-GBW amplified has a transition frequency f_T of 38 kHz (including the gain stage, A), a power consumption of 150 nW, a phase margin (PM) of ≈70°, an area of 300×36 μm², and a minimum current per transistor of 7 nA, which is far above the leakage current after irradiation. The complete circuit was implemented in the radiation hard SOI-SIMOX BiCMOS-PJFET technology of DMILL     

Micropower fully integrated CMOS readout interface for neural recording application

In this paper, we presented a micropower, small-size fully integrated CMOS readout interface for neural recording system. A crucial and important module of this system is the amplifier circuit with low-power low-noise. We describe a micropower low-noise readout circuit using an active feedback fully differential structure to reject the 1/f noise and large DC-offsets, the substrate-bias technology to further decrease the noise and power of the neural recording amplifier. Therefore, the neural amplifier with micropower low-noise and high input impedance is presented. The readout interface core, fully differential amplifier is implemented in 0.35-μm CMOS process, passes neural signals from 10 Hz to 9 kHz with an input-referred noise of 4.3 μV_rms. The power consumption of single amplifier is 5.6 μW while consuming 0.03 mm² of die area. The low cutoff frequencies of the circuit can adjusted from 10 Hz to 400 Hz, and the high cutoff frequencies form 4 kHz to 9 kHz.     

Low-noise differential transimpedance amplifier structure based on capacitor cross-coupled gm-boosting scheme

This paper presents a capacitor cross-coupled g_m-boosting scheme for differential implementation of common-gate transimpedance amplifier (CG-TIA). A differential transimpedance amplifiers (DTIA) is designed by this scheme using two modified floating-biased CG stage with improved low corner frequency. Despite conventional methods for single-ended to differential conversion that increase the power and the noise for the same gain, the new DTIA gives a higher gain and hence reduces the input-referred noise power. Design of the DTIA circuit using 0.13 μm CMOS technology illustrates near 1.7 dB improvement in the circuit sensitivity and 5.2 dB enhancement in transimpedance gain compared to its single-ended counterpart. Operation at very low frequencies and stable dc coupling to photodiode are other features of the proposed DTIA.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

Design of low power UWB LNA based on common source topology with current-reused technique

This paper presents two low power UWB LNAs with common source topology. The power reduction is achieved by the current-reused technique. The gain and noise enhancement of the proposed circuit is based on an output buffer which is used by a common source amplifier with shunt–shunt feedback. Chip1 is an adopted T-match input network of 50 Ω matching in the required band. Measurements show that the S₁₁ and S₂₂ are less than −10 dB, and the maximum amplifier gain S₂₁ gives 9.7 dB, and the noise figure is 4.2 dB, the IIP3 is −8.5 dBm, and the power consumption is 11 mW from 1.1 V supply voltage. The input matching of chip2 is adopted from a LC high pass filter and source degenerated inductor. The output buffer with the RC-feedback topology can improve the gain, increase the IIP3, restrain the noise, improve the noise figure and decrease the DC power dissipation. Measurements show 13.2 dB of power gain, 3.33 dB of noise figure, and the IIP3 is −3.3 dBm. It consumes 9.3 mW from 1.5 V supply voltage. These two chips are implemented in a 0.18 μm TSMC CMOS process.     

A multimode digital detector readout for solid-state medicalimaging detectors

A multipurpose digital detector readout for medical imaging applications is presented. The readout is capable of measuring both current and charge, allowing a single detector array to perform imaging functions previously accomplished with two separate machines. The circuit employs a variable rate ΣΔ analog-to-digital converter (ADC) to measure current over a 130-dB dynamic range in a 1 kHz band and resolve charge pulses down to 360 e^- at 100 000 events/s. Detector currents of up to 7 μA and charge pulses as large as 25 fC can be measured. A low-noise charge sensing amplifier (CSA) is combined with digital pulse shaping to optimize the noise performance and flexibility of the charge measurements. Fabricated in an 1.2 μm complimentary metal-oxide-semiconductor (CMOS), the circuit occupies 1.5 mm² and dissipates 11 mW/channel from a 5 V supply     

A Small Area Charge Sensitive Readout Chain with a Dual Mode of Operation

A charge sensitive readout chain has been designed and fabricated in acommercially available 0.8 m CMOS technology. The readout chain is optimizedfor pixel detectors measuring soft X-ray energies up to 20 KeV. In the first modean analog signal proportional to input charge is generated and processed in realtime. In the second mode a peak-and-hold operation is enabled and therelevant signal is processed in later time. This dual mode of operation iscontrolled by an external digital signal. The readout chain consists of a chargeamplifier, a shaper, an operational amplifier which can either operate as avoltage amplifier or a peak detector and an output buffer. Its area is . The gain at the shaper output is 378 mv/fC, theENC is 16 rms at 160 nsec shaping time. The overall gainis 557 mV/fC, the ENC is rms with 240 nsec peaking timeand 1.4 sec recovery time. The overall power dissipation is 1.5 mWatt with aload capacitance of 25 pF.     

Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

HgCdTe柔性中波红外探测器放大电路设计及噪声分析

设计了一种应用于HgCdTe柔性中波红外探测器的微弱信号放大电路,该电路由电桥电路、调零电路及滤波电路组成.采用平衡电桥与仪表运算放大器INA333相结合的方式搭建电桥电路;并针对探测器直流分量过大问题,设计了可调零、带增益的信号处理电路;最后通过由二阶有源滤波器组成的滤波电路将高频噪声滤除.利用运算放大器的En-In噪声模型,对放大电路进行了噪声分析,并测试了探测器在弯曲状态下的响应性能.实验结果表明,所设计的放大电路增益为86 dB,噪声均方根值低于6.1 mV;柔性探测器的曲率半径为3 mm;当探测器光敏面上的光谱辐照功率为6.75×10-7 W时,产生的光电信号约102?V.     

Low-cost test technique using a new RF BIST circuit for 4.5-5.5 GHz low noise amplifiers

This paper presents a low-cost test technique using a new RF Built-In Self-Test (BIST) circuit for 4.5-5.5 GHz low noise amplifiers (LNAs). The test technique measures input impedance, voltage gain, noise figure, input return loss and output signal-to-noise ratio of the LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The BIST circuit contains test amplifier and RF peak detectors. The complete measurement set-up contains LNA with BIST circuit, external RF source, RF relays, 50 Ω load impedance, and a DC voltmeter. The test technique utilizes output DC voltage measurements and these measured values are translated to the LNA specifications such as input impedance and gain through the developed equations. The technique is simple and inexpensive.     

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18 μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6 GHz. The resonance points were set in 3 GHz and 10 GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S₂₁>10 dB) with a good input impedance matching less than –10 dB and a minimum noise figure of 2.9 dB over the entire band. The proposed UWB LNA consumed 15.2 mW from a 1.8 V power supply.     

CMOS宽带可变增益放大器

设计了一种CMOS宽带、低功耗可变增益放大器.在分析使用源极退化电阻的共源放大器高频特性基础上,通过加入频率补偿电容改变放大器的零极点分布,在不增加功耗的情况下扩展了带宽.分析了放大器在低增益下出现的增益尖峰现象并加以解决.使用跨导增强电路提高了放大器的线性度.两级可变增益放大器使用TSMC0.25μm CMOS工艺.仿真结果表明,放大器在3.3V电压下核心电路功耗为3.15mW,增益范围0～40dB;在负载为5pF电容时3dB带宽大于340MHz,输出三阶交调点高于3.5dBm.