Nanowire Crossbar Logic and Standard Cell-Based Integration

Nanowire crossbar is one of the most promising circuit solutions for nanoelectronics. However, it is still unclear whether or how they can be competitive in implementing logic circuits, as compared to their MOSFET counterparts. We analyze nanowire crossbars in area, speed, and power, in comparison with their MOSFET counterparts. We show nanowire crossbars do not scale well in terms of logic density and speed. To achieve performance close to their MOSFET counterparts, crossbar circuits need faster field-effect transistors (FETs) to compensate the high resistance of nanowires. Motivated by the analysis and comparative study, we propose a crossbar cells design based on judicious use of silicon nanowires. The crossbar cell is compatible with the conventional MOSFET fabrication and design methodologies, in particular, standard cell-based integrated circuit design. We evaluate logic circuits synthesized with crossbar cells and MOSFET cells based on the MCNC91 benchmark. The results show that crossbar cells can provide a density advantage of more than four times over the traditional MOSFET circuits with the same process technology, while achieving close performance and consuming less than one third power.      

A novel digital logic implementation approach on nanocrossbar arrays using memristor-based multiplexers

This paper presents and evaluates a novel multiplexer (MUX) composed of memristive devices and nanowire crossbar arrays. The switching behavior of memristors is employed to reveal the desired output state. By applying a sequence of appropriate voltage pulses to the developed MUX, the output is derived and can be transferred through read/write CMOS circuitry. The performance is verified with the SPICE simulator including a threshold-type memristor model. Using the proposed MUXes instead of memristor-based NAND gates, the routing effects that are a major challenge for implementing combinational logic in hybrid circuits can be reduced. Our evaluation results show that both density and delay are effectively improved in pure-MUX-based fabrics.     

判奇电路实现方法探讨

以三输入判奇电路设计为例,通过对其输出函数表达式的形式变换,分别采用多种门电路及译码器、数据选择器等74系列器件进行电路设计,给出了7种电路实现形式,并分析了各种电路实现的优缺点。此例说明了组合逻辑电路设计的灵活性及电路实现的多样性。所采用的设计方法对其他组合逻辑电路设计具有一定的启发与指导意义。     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

A coded 8-PSK system for 140 Mb/s information rate transmission over 80 MHz non-linear transponders

A combined 8-PSK modulation and rate 7/9 convolutional coding technique is proposed for 140 Mb/s information rate transmission over the 80 MHz INTELSAT transponders, thus achieving a bandwidth efficiency of 1.75 b/s/Hz of allocated bandwidth. The desired power efficiency is to achieve a bit error rate of 10^?6 at an E_b/N₀ of 11 dB, including modem and codec implementation losses. The proposed system employs an 8-PSK modem operating at a 60 MHz symbol rate (or 180 Mb/s bit rate), as well as a rate 7/9 convolutional encoder and a 16-state Viterbi algorithm decoder operating at 60 MHz. The rate 7/9 code is periodically time varying and is designed to maximize the Euclidean distance between the modulated codeword sequences, thereby achieving a 3 dB asymptotic coding gain relative to the conventional QPSK system over an AWGN channel. This code is also designed to reduce decoder complexity for high-speed operations. The performance of the proposed system over INTELSAT V and VI non-linear transponders was evaluated by Monte Carlo computer simulation. The 180 Mb/s 8 PSK modem, including the automatic frequency control, automatic gain control, carrier recovery and clock recovery circuits, has been implemented and tested. The complete Viterbi decoder is being implemented on five boards, and the critical add-compare-select (ACS) circuit of the high-speed Viterbi algorithm decoder is being implemented with hybrid technology employing 100-K series emitter-coupled logic dies on specially designed ceramic substrates. The ACS circuit operates at a speed exceeding 120 MHz, well over the design goal of 60 MHz. Construction of this codec is almost complete.     

BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)

In-Memory computation has received considerable attention in the light of recent advances made in the memristor-based design. Non-volatile memristor devices are compatible with both the crossbar structure, CMOS technology, and can perform logical operations when subjected to suitable voltages. In this work, a generalized synthesis technique is presented to implement the logic functions inside pure memristive-crossbar. To initiate the process, two novel memristive-designs are proposed for 2:1 multiplexer (MUX) that follow Memristor Aided loGIC (MAGIC) design style. Experimental results showed that each design is at least 68.05 %, 35.92 % more energy-efficient than their existing IMPLY, MAGIC-based designs, respectively. One of our proposed MUX designs is optimized in memristor-count, and the other is latency-optimized. The latency-optimized design offers 20 % improvement in performance compared to its existing IMPLY, MAGIC-based peers. Based on the simulation methodology presented in this work, the memristive-MUXes are simulated in Cadence Virtuoso. Subsequently, our proposed MUX designs are used for the technology mapping of the nodes of the Binary Decision Diagrams (optimized in terms of node, path counts) for the logic functions. Our proposed technique optimizes the implemented logic circuits in terms of memristor-count, step-count, and provides the details for – latency, required memristors, energy, area. Comparison of the synthesis results showed that the circuits generated using our proposed MAGIC-MUXes, are at least 82.21 %, 44 % more energy-efficient, and can offer 18.94 %, 18.92 % more performance-improvements than their peers, realized using the existing IMPLY, MAGIC-MUX designs, respectively. Also, our proposed-MUX based circuits need at least 56.73 % lesser crossbar-areas than their existing MAGIC-MUX based peers, which indicates the scope for large scale parallel processing inside a given memristive-memory.     

Configurable memristive logic block for memristive-based FPGA architectures

This article proposes a Configurable Memristive Logic Block (CMLB) that comprises of novel memristive logic cells. The memristive logic cells are constructed from memristive D flip-flop, 6-bit non-volatile look-up table (NVLUT), and multiplexers. The memristive logic cells are interconnected using memristive switch matrix cells to form the CMLB. The CMLB is then used to construct a memristor-based FPGA architecture. The proposed CMLB shows a reduction of 8.6% of device area and 1.094 times lesser critical path delay against the SRAM-based FPGA architecture. Against similar CMOS-based circuits, the memristive D flip-flop provides switching speed of 1.08 times faster, the NVLUT reduces power consumption by 6.25 nW, and the memristive logic cells reduce device area by 60.416 µm². In this research work also, various memristor-based FPGA architectures found in the literature are compared against the SRAM-based FPGA architecture.     

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger

In VLSIs, soft errors resulting from radiation-induced transient pulses frequently occur. In recent high-density and low-power VLSIs, the operation of systems is seriously affected by not only soft errors occurring on memory systems and the latches of logic circuits but also those occurring on the combinational parts of logic circuits. The existing tolerant methods for soft errors on the combinational parts do not provide enough high tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and a pass transistor. The paper also presents a construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, simulation results show that the proposed method has higher soft error tolerant capability than the existing methods. For supply voltage V _DD ?=?3.3 V, the proposed method is capable of masking transient pulses of magnitude 4.0 V or less.     

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single-event transients (SETs) before they can be captured in latches or flip-flops. TTFs are tuned by adjusting the maximum width of the propagated SET that can be suppressed. A TTF requires 6–14 transistors, making it an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-V _DD and gate sizing is described. Simulation results for the 65 nm process technology indicate that a 17–48× reduction in the soft error rate can be achieved with this approach.     

Fast multiplication in VLSI using wave pipelining techniques

Wave pipelining is a design methodology that can increase the clock frequency of digital systems. Also known asmaximum-rate pipelining, it has long been considered a technique for approaching the physical speed limit of a digital circuit. Unlike conventional pipelining, wave pipelining does not require internal clocked elements to increase throughput. The synchronization of internal computations is achieved by balancing inherent RC delays of combinational logic elements, thus allowing circuits to be pipelined at a very fine-grain level. In this article, we describe the design of a 16×16 wave-pipelined multiplier using a 1.0 μm CMOS process. The multiplier is designed using a conventional static CMOS technology. Simulation results show a speedup of about 7× over a nonpipeline implementation.     

CPLD实现雷达自动增益控制的优化

复杂的可编程逻辑器件可以完成较大规模的组合逻辑电路设计，提高系统的集成化。本文介绍了复杂可编程逻辑器件和电路设计的一般流程，以及数字自动增益控制电路的组成和采用CPLD设计的实现。     

A leakage reduction methodology for distributed MTCMOS

Multithreshold CMOS (MTCMOS) circuits reduce standby leakage power with low delay overhead. Most MTCMOS designs cut off the power to large blocks of logic using large sleep transistors. Locally distributing sleep devices has remained less popular even though it has several advantages described in this paper. However, locally placed sleep devices are only feasible if sneak leakage currents are prevented. This paper makes two contributions to leakage reduction. First, we examine the causes of sneak leakage paths and propose a design methodology that enables local insertion of sleep devices for sequential and combinational circuits. A set of design rules allows designers to prevent most sneak leakage paths. A fabricated 0.13-/spl mu/m, dual V/sub T/ test chip employs our methodology to implement a low-power FPGA architecture with gate-level sleep FETs and over 8/spl times/ measured standby current reduction. Second, we describe the implementation and benefits of local sleep regions in our design and examine the interfacing issues for this technique. Local sleep regions reduce leakage in unused circuit components at a local level while the surrounding circuits remain active. Measured results show that local sleep regions reduce leakage in active configurable logic blocks (CLBs) on our chip by up to 2.2/spl times/ (measured) based on configuration.     

Design a Low-Power H.264/AVC Baseline Decoder at All Abstraction Levels—A Showcase

In this paper, we propose a low-power VLSI implementation of H.264/AVC baseline decoder. A systematic methodology for power reduction is proposed and applied at various design abstraction levels. At the algorithm level, the computational complexity is optimized. At the architecture level, pipelining and parallelism are widely adopted to reduce the operating frequency; hierarchical memory organization optimizes power-hungry memory accesses; hardware sharing reduces the total switching capacitance. At the circuit level, the knowledge about signal statistics is exploited to reduce number of transitions; data dependent signal-gating and clock-gating are introduced which are dynamic techniques for power reduction; multiplications are reduced and optimized, while complex dividers are totally eliminated. At the physical level, cell sizing and layout are optimized for power efficiency. The VLSI implementation shows that with UMC 0.18 μm technology, the proposed design is able to decode realtime QCIF 30fps at 1.5 MHz. The decoder contains 169 k logic gates and 2.5 KB on-chip SRAM. The total chip area is 4.4 × 4.4 mm² in a CQFP 208 package. The measured power consumption is 973 μW @ 1.8 V and 293 μW @ 1.0 V. The low-power and realtime features make our design ideal for portable or mobile applications.     

Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits’ combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection method based on gate sizing, called Weighted and Timing Aware Gate Sizing (WTAGS). Unlike the previous techniques that either overlook internal nodes signal probability or exploit fault injection, ECIP computes the sensitivity of each gate by analytical calculations of both the probability of transient pulse generation and the probability of transient pulse propagation; these calculations are based on signal probability of the whole circuit nodes which make ECIP much more accurate as well as practical for large circuits. Using the results of ECIP, WTAGS characterizes the most sensitive gates to efficiently allocate the redundancy budget. The simulation results show the SER reduction of about 40% by applying the proposed method to ISCAS’89 benchmark circuits while imposing no delay overhead and 5% area overhead.     

Delay-insensitive gate-level pipelining

Gate-level pipelining (GLP) techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL convention logic (NCL). Pipelined NCL systems consists of combinational, registration, and completion circuits implemented using threshold gates equipped with hysteresis behavior. NCL combinational circuits provide the desired processing behavior between asynchronous registers that regulate wavefront propagation. NCL completion logic detects completed DATA or NULL output sets from each register stage. GLP techniques cascade registration and completion elements to systematically partition a combinational circuit and allow controlled overlapping of input wavefronts. Both full-word and bit-wise completion strategies are applied progressively to select the optimal size grouping of operand and output data bits. To illustrate the methodology, GLP is applied to a case study of a 4-bit×4-bit unsigned multiplier, yielding a speedup of 2.25 over the non-pipelined version, while maintaining delay insensitivity.     

A survey of efficient MDCT implementations in MP3 audio coding standard: Retrospective and state-of-the-art

This tutorial paper describes various efficient implementations (published and new unpublished) of the forward and backward modified discrete cosine transform (MDCT) in the MPEG layer III (MP3) audio coding standard developed in the time period 1990-2010, including the efficient implementation of polyphase filter banks for completeness. The efficient MDCT implementations are discussed in the context of (fast) complete analysis/synthesis MDCT filter banks in the MP3 encoder and decoder. In general, for each efficient forward/backward MDCT block transforms implementation are presented: complete formulas or sparse matrix factorizations of the algorithm, the corresponding signal flow graph for the short audio block and the total arithmetic complexity as well as the useful comments related to improving the arithmetic complexity and a possible structural simplification of the algorithm. Finally, all efficient forward/backward MDCT implementations are compared both in terms of the arithmetic complexity and structural simplicity. It is important to note that almost all presented algorithms can be also used for the 2ⁿ-length data blocks in others MPEG audio coding standards and proprietary audio compression algorithms.     

Defect-tolerant Logic with Nanoscale Crossbar Circuits

Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies for molecular electronics introduce numerous defects so insisting on defect-free crossbars would give unacceptably low yields. Instead, increasing the area of the crossbar provides enough redundancy to implement circuits in spite of the defects. We identify reliability thresholds in the ability of defective crossbars to implement boolean logic. These thresholds vary among different implementations of the same logical formula, allowing molecular circuit designers to trade-off reliability, circuit area, crossbar geometry and the computational complexity of locating functional components. We illustrate these choices for binary adders. For instance, one adder implementation yields functioning circuits 90% of the time with 30% defective crossbar junctions using an area only 1.8 times larger than the minimum required for a defect-free crossbar. We also describe an algorithm for locating a combination of functional junctions that can implement an adder circuit in a defective crossbar.     

SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET

In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable operation of integrated circuits. This paper presents a novel design style which reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. The independent design style of this method achieves SET mitigation and noise immunity by strengthening the sensitive nodes using a technique similar to feedback. A realization for this methodology is presented in 7 nm FinFET and in order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability as well as better noise immunity.     

mMIG: Inversion optimization in majority inverter graph with minority operations

Majority inverter graph is a logic representation structure that along with its algebraic properties synthesizes circuits with improved area, delay, and speed metrics, as compared to conventional And-Invert graph (AIG) realization. In this paper, we propose mMIG synthesis approach, where we aim to minimize the number of inverters in such circuits by adopting minority logic in addition to majority and inversion operations in the logic representation. We propose a set of Boolean transformation methods and derived theorems for minority, majority, and inverter operations. We demonstrate that minority operation in addition to majority and inversion operations significantly optimizes the hardware footprint of combinational circuits and cryptographic primitives, such as linear operations and substitution boxes in several lightweight block ciphers. The area optimization is considered with reduction in count of complemented edges or inversion operations. As results demonstrate, the inversion operations have been reduced from 57.7% to 93.3% in mMIG synthesis approach as compared to MIG logic synthesis in EPFL combinational benchmark suite. In round function implementations of lightweight block ciphers such as SIMON, and ARX boxes such as MARX-2 and SPECKEY, the count of complemented edges in mMIG synthesis technique has been reduced by almost 50% as compared to that in MIG based implementations.     

Quaternary logic circuits in 2-μm CMOS technology

Novel quaternary logic circuits, designed in 2-μm CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra has been designed and fabricated. The prototype chip occupies an area of 4.84 mm², is timed with a 2.2-MHz clock, and consumes 93 mW of power