Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process

A novel Substrate-Engineered Gate-Grounded NMOS (GGNMOS) structure with very low trigger voltage is proposed to protect the ultra-thin gate oxide effectively in nanoscaled integrated circuits. This device is designed and verified in a 65 nm CMOS process. With increased substrate resistance and pumped triggering current provided by power bus controlled PMOS, this structure features a significantly reduced trigger voltage of 2.8 V and an enhanced uniform conduction of multi-fingers. The failure current can be improved by 23.5% compared with traditional GGNMOS.     

ESD protection for thin gate oxides in 65 nm

Unexpected functional failures were found in the core of an IC, processed in a 65 nm technology with 1.8 nm gate oxide, after Machine Model (MM) testing, although a comprehensive rail-based protection scheme was applied. Failure analysis was performed including Obirch, backside de-processing, and SEM analysis to locate the failure in the gate oxide of several core NMOS transistors. Careful Transmission Line Pulse (TLP) measurements on NMOSTs with 1.8 nm oxides yields a mean BVox = 6.06 V and standard deviation of 0.18 V, after correction for MM test conditions. Comparison with a mean Vt1 = 5.35 V and a standard deviation of 0.15 V for ggNMOSTs shows that the tails of the BVox and Vt1 distributions overlap. This implies that connecting a gate to a drain diffusion does not guarantee adequate protection for a 1.8 nm gate oxide in a 65 nm technology.     

Full-chip leakage analysis for 65 nm CMOS technology and beyond

This work proposes a full-chip leakage analysis framework for 65 nm technology and beyond. Analytical models are first constructed to capture the impact of process parameters on leakage current. Then a methodology is introduced to characterize leakage-related process variations in a systematic manner. On such a basis, an efficient procedure is developed to analyze the state-dependent power dissipation due to leakage of a large circuit block by taking into account different leakage mechanisms. Unlike many traditional approaches that rely on log-normal approximations, the proposed algorithm applies a quadratic model of the logarithm for the full-chip leakage current. It is able to handle both Gaussian and non-Gaussian parameter distributions. The model is validated with test chips manufactured with a commercial 65 nm CMOS process. Validation results prove that the proposed modeling methodology could achieve a higher accuracy than that from existing methods. Moreover, a full-chip leakage analysis using the developed model can be orders of magnitude faster than a Monte Carlo based approach.     

The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs

The holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the LCD driver ICs to be susceptible to the latchup-like danger in the practical system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-/spl mu/m 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with power supply of 40 V.     

A broadband RF 65 nm CMOS front-end for cable TV reception

A novel broadband RF front-end in 65 nm CMOS technology is presented. The front-end serves to precondition the incoming RF spectrum for further processing in a cable TV receiver architecture where RF channel selection and down conversion are done in digital domain. The analog front-end consists of a broadband highly linear low-noise amplifier followed by a variable gain RF amplifier. An original broadband circuit topology for the amplifiers is adopted.The fabricated front-end exhibits a bandwidth of 50-1050 MHz, a variable gain, which spans from 12 to 37 dB with a 0.2 dB step, an OIP3 of 28.4 dBm (77.5 dBmV), an OIP2 of 65 dBm (114 dBmV), and a noise figure of 5.8 dB, dissipating 125 mW at 1.2 V supply, and a core silicon area of 0.4 mm².     

90纳米CMOS工艺下带改进RC网络的电源轨静电泄放箝位电路

An electrostatic discharge(ESD) detection circuit with a modified RC network for a 90-nm process clamp circuit is proposed.The leakage current is reduced to 4.6 nA at 25℃.Under the ESD event,it injects a 38.7 mA trigger current into the P-substrate to trigger SCR,and SCR can be turned on the discharge of the ESD energy.The capacitor area used is only 4.2μm~2.The simulation result shows that the proposed circuit can save power consumption and layout area when achieving the same trigger efficiency,compared with the previous circuits.     

A 77 GHz FMCW radar transmitter with reconfigurable power amplifier in 65 nm CMOS

A frequency modulated continuous-wave (FMCW) radar transmitter in 65 nm CMOS is presented. The transmitter consists of one FMCW signal generator, one reconfigurable power amplifier and bias circuits. FMCW chirp signal comes from a sigma-delta modulated fractional-N phase-locked loop (PLL) with an integrated digital triangle-wave generator to control the output division-ratio of the sigma-delta modulator. A four-way power combining power amplifier is employed to improve the output power with a reconfigurable output power to satisfy different detection distance requirements. The measured results show that the chirp bandwidth achieves 2 GHz, from 76 GHz to 78 GHz, and the power amplifier achieves 13.1 dBm output P1dB with 8.1% PAE. The power amplifier and FMCW signal generator consume 228 mW and 56 mW power, respectively, with a 1.0 V power supply. The core die area is only 2.6×0.88 mm².     

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.     

ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology

This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the human-body-model (HBM) ESD level of this new proposed I/O cells can be greater than 5 kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of the I/O cell.     

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

This paper presents an 8×8 bit pipelined multiplier operating at 320 MHz under 0.5 V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5 V. The proposed pipelined multiplier is fabricated in 130 nm CMOS process. It operates up to 320 MHz and the power consumption is only 1.48 mW at 0.5 V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5 V is reduced over 5.7 times than that of the traditional architecture at 1.2 V. Thus, the proposed 8×8 bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.     

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.     

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant

Electrical and SEM analysis of gate-silicided (GS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism changes from source-to-drain filamentation to drain-to-substrate short when a p-type ESD implant (ED) is used. Simulations show that the reason for change in failure mode is the different current and temperature distribution when the device is operated in bipolar mode due to the presence of ED. The size of the drain silicide blocking can be reduced from 3 to 0.75 μm by the use of ED while keeeping the same ESD failure current with the corresponding area saving benefit. When the ED implant extends under the drain contacts, the on-resistance (Ron) of the device can be reduced by 50% with respect to a design where ED is not located under the contacts.     

Impact of process parameters on circuit performance for the 32 nm technology node

As IC dimensions scale down to the 32 nm technology node, interconnect is more than ever the most limiting factor affecting overall circuit performance. The influence of all involved process parameters were studied as a function of target application through electromagnetic and time domain simulations, and compared to the impact of driver characteristics. As a result, an optimization of the BEOL stack was performed to propose process and material recommendations meeting electrical specifications for most circuit applications.     

A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS

A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65 nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are −0.4/0.4 LSBs and −0.9/0.8 LSBs, respectively. At 660 MS/s sampling rate, the ADC consumes 7.6 mW from a 1.2 V supply. The proposed SAR ADC?s SNDR and SFDR are 49.5 dB and 64.2 dB, respectively.     

65nm CMOS工艺下新型静电防护衬底改造GGNMOS

为实现纳米集成电路上(On-Chip)的静电(ESD)防护,有效保护脆弱的栅氧,基于65 nm CMOS工艺,提出使用增大衬底电阻技术以及电源轨控制辅助PMOS提供额外触发电流技术的新型衬底改造GGNMOS.测试结果表明,与传统GGNMOS结构相比,新型结构具有低触发电压(3V)以及更高的失效电流(增加23.5％)等优点.     

An optimal silicidation technique for electrostatic discharge protection sub-100 nm CMOS devices in VLSI circuit

In this paper we propose a silicide design consideration for electrostatic discharge (ESD) protection in nanoscale CMOS devices. According to our practical implementation, it is found that a comprehensive silicide optimization can be achieved on the gate, drain, and source sides with very few testkey designs. Our study shows that there is a high characteristic efficiency for various conditions; in particular, for optimizing the performance of sub-100 nm complementary metal-oxide-semiconductor devices in system-on-a-chip era.     

High-speed reduced-leakage SRAM memory cell design techniques for low-power 65 nm FD-SOI/SON CMOS technology

The paper presents a detailed study on the sub-1 V high speed operation with reduced leakage design techniques for conventional 6T Static Random Access Memory (SRAM) on fully depleted Silicon-on Insulator (FD-SOI) and fully depleted Silicon-on-Nothing (FD-SON) technology. Performance of SON MOSFET is found to be significantly better both in terms of power and speed from its equivalent SOI device. Future devices with advanced technology are promising for low-power application. The most promising high-speed, low-power operation techniques are introduced, analyzed and compared into 65 nm low-power FD-SOI/SON technology. Hspice simulations conclude Drive Source Line (DSL) architecture as the best option for high speed operation in sub 100 nm technology without affecting the Static Noise Margin (SNM) of the cells.     

Design on the low-leakage diode string for using in the power-railESD clamp circuits in a 0.35-μm silicide CMOS process

A new design of the diode string with very low leakage current is proposed for use in the ESD clamp circuits across the power rails. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new diode string with six stacked diodes at 5 V (3.3 V) forward bias can be reduced to only 2.1 (1.07) nA at a temperature of 125°C in a 0.35 μm silicide CMOS process, whereas the previous designs have a leakage current in the order of mA. The total blocking voltage of this new design with NCLSCR can be linearly adjusted by changing the number of the stacked diodes in the diode string without causing latch-up danger across the power rails. From the experimental results, the human-body-model ESD level of the ESD clamp circuit with the proposed low-leakage diode string is greater than 8 kV in a 0.35 μm silicide CMOS process by using neither ESD implantation nor the silicide-blocking process modifications     

Digitally assisted neural recording and spike detection multichannel integrated circuit designed in 180 nm CMOS technology

This paper presents design and measurement results of an integrated circuit dedicated to recording and detecting a wide range of biomedical signals. The chip is designed in 180 nm CMOS technology and occupies 1.5×1.5 mm². It consists of 8 channels responsible for amplification, filtration and detection of biomedical signals. In order to satisfy the requirements of a wide range of neurobiological experiments, the main parameters of a single recording channel, such as voltage gain, frequency band, voltage offset and threshold detection, are controlled independently by on-chip digital registers. The recording part is divided into two separate channels, i.e. an Action Potential (AP) stage and a Local Field Potential (LFP) stage. The voltage gain of the AP and LFP stages can be switched between 55.7/50.3 dB and 50.3/45.1 dB respectively. Corner frequencies of a particular stage can be digitally controlled in a wide range, i.e. the upper cut-off frequency can be changed in the 20 Hz–2 kHz (LFP stage) while the lower cut-off frequency can be tuned at the 120 mHz–3 kHz (LFP and AP stage). The upper cut-off frequency of the AP stage is equal to 6.9 kHz. In addition, the area of the analog part of the recording channel is 0.04 mm². A single recording channel is supplied from ±0.9 V and consumes about 4.8 µW of power while the Input Referred Noise is equal to 6.2 µV resulting in 4.92 of Noise Efficiency Factor (NEF).     

A 65 nm CMOS fully-integrated dynamic reconfigurable differential power amplifier with high gain in both bands

A fully-integrated dual-band dynamic reconfigurable differential power amplifier with high gain in 65 nm CMOS is presented. A switchable shunt LC network is proposed to implement the dual-band reconfigurable operation and achieve high gain at both low and high frequency bands, and the high quality on-chip transformers are utilized to implement input/output impedance matching and single-ended to differential conversion. Measured results show that the dual-band dynamic reconfigurable power amplifier can provide 23 dB gain at 2.15 GHz and 21 dB gain at 4.70 GHz, and achieve more than 19 dBm saturated output power at 2.15 GHz and 13 dBm saturated output power at 4.70 GHz, respectively. The die area is about 1.7 mm×2.0 mm.