A dual-gate 2nd/3rd-order subharmonic injection-locked oscillator in GaAs PHEMT

A dual-gate subharmonic injection-locked oscillator (SILO) has been designed and fabricated in 0.5 μm GaAs PHEMT process for millimeter-wave communication applications. Specifically, this study proposes a dual-gate circuit topology to achieve a high-frequency oscillator with a large output signal power. The proposed dual-gate transistor also performs a wideband negative resistance characteristic by which the self-oscillation frequency can easily be determined with a proper resonator. The measured self-oscillation frequency of the proposed SILO is approximately 49 GHz, and the frequency tuning range is adjustable from 48.7 GHz to 49.7 GHz with an output power of 8 dBm. By injecting a 2nd-order (~24.5 GHz) subharmonic signal into the dual-gate SILO, the maximum locking range of 5.6 GHz can be approached at an input power of 11 dBm without any self-oscillation frequency tuning. With changing the input frequency to be a 3rd-order subharmonic injection (~16.3 GHz), an output locking range of 2.9 GHz also can be achieved. The measured phase noises of the output signals from 2nd- and 3rd-order subharmonic injections are −101 and −100 dBc/Hz, respectively, at 100-kHz offset frequency.     

A wide band differentially switch-tuned CMOS monolithic quadrature VCO with a low Kvco and high linearity

A wide band, differentially switch-tuned CMOS monolithic LC-VCO is presented in this paper, as well as a frequency divider for high linearity, low Kvco quadrature signal generation. A linearity control logic is proposed. The Kvco linearity is improved to be lower than 17.68 MHz/V. By using the proposed CML DFF, the operating frequency of the frequency divider is increased by 20% with a power consumption of 3.6 mW. The proposed design has been fabricated and verified in a 0.18 μm CMOS process. The QVCO is tuned in a combined way of continuous technology and 4 bit binary switch capacitor array (SCA) discrete tuning technology. The measurement indicates that the QVCO has a 19.7% tuning range from 1.816 to 2.213 GHz. The measured phase noise is −112.25 dBc/Hz at 1 MHz offset from the 1.819 GHz carrier and draws a current of 4.0 mA around at a 1.8 V supply.     

A cross coupled low phase noise oscillator using an output swing enhancement technique

A new voltage controlled oscillator (VCO) in a 0.18 μm CMOS process is offered in this paper. This paper?s argument is to provide an innovative approach to improve the phase noise which is one of the most controversial issues in VCOs. Contrary to most ideas that have been put forward to decrease phase noise which are based on higher current dissipation to increase output voltage swing, this new method offers better specifications with respect to traditional solutions. The presented circuit is capable of extra oscillation amplitude without increasing the current level, taking advantages of tail current elimination and topology optimization. Analysis of the presented peak voltage amplitude can verify the optimum performance of the proposed. Post-layout simulation results at 2.3 GHz with an offset frequency of 1 MHz and 3 MHz show a phase noise of about −125 dBc/Hz and −136.5 dBc/Hz, respectively, with the current of 1.3 mA from 1.8 V supply. Also, Monte Carlo simulation is used to ensure the sensitivity of the proposed circuit to process and frequency variations are very promising.     

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18 μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6 GHz. The resonance points were set in 3 GHz and 10 GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S₂₁>10 dB) with a good input impedance matching less than –10 dB and a minimum noise figure of 2.9 dB over the entire band. The proposed UWB LNA consumed 15.2 mW from a 1.8 V power supply.     

Design of a tunable multi-band differential LC VCO using 0.35 μm SiGe BiCMOS technology for multi-standard wireless communication systems

In this paper, an integrated 2.2-5.7 GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 μm SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and −6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as −37.21 and −47.6 dBm, respectively. The phase noise between −110.45 and −122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between −176.48 and −181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between −6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm² on Si substrate, including DC, digital and RF pads.     

Design of self-bias tail transistor technique for low phase noise CMOS VCO with harmonic suppression using capacitance ground

This paper presents a low phase noise wideband CMOS VCO based on the self-bias tail transistor technique and harmonic suppression using a capacitance ground. This VCO utilizes switching capacitor arrays in which four channels are able to be selected for multi-band application. Moreover, the design of CMOS VCO makes good use of the self-bias tail transistor and capacitance ground filter technique to reduce the phase noise. The MOS varactors are used as fine tuning for wideband operating application. The fully integrated VCO provides excellent performance with high FOM −193 dBc/Hz. The bandwidth of the frequency is 1.1 GHz and the tuning range is 13.8%. The power dissipation of the core circuit is 8.28 mW under a 1.8 V supply and phase noise is measured as low as −123.6 dBc/Hz at 1 MHz offset under 8.5 GHz oscillation frequencies. This VCO was made by the TSMC 0.18 μm 1P6M CMOS standard process and the chip area is 0.75×0.69 (mm²).     

A 0.35 μm CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage-current feedback topology

This paper presents a new divide-by-2 quadrature injection-locked frequency divider (QILFD). The QILFD consists of a new transformer-coupled quadrature voltage controlled oscillator (QVCO) with the voltage-current feedback technique and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS QILFD has been implemented with the TSMC 0.35 μm CMOS technology and the core power consumption is 16.52 mW at the supply voltage of 2.2 V. The free-running frequency of the QILFD is tunable from 2.85 GHz to 3.07 GHz. At the input power of 0 dBm, the divide-by-2 operation range is from 5.48 GHz to 6.48 GHz. The phase deviation of free running quadrature output is about 0.53°.     

Design of a 30 GHz rotary traveling wave oscillator with improved frequency tuning range in 0.18 μm CMOS technology

In this paper, the operation of rotary traveling wave oscillators is analyzed, the general oscillation condition is derived, and analytical formula for the oscillator loss is presented. Based on this analysis, switched transmission line is employed to extend the output frequency tuning range. Post-layout simulation shows a frequency tuning range of 3.1 GHz in the vicinity of 30 GHz. The proposed half-quadrature VCO exhibits a phase noise better than −102.2 dBc/Hz at 1 MHz offset frequency. The VCO provides an output power level ranging from −6 to −2.5 dBm with drawing 15.2 mA of dc current from a 1.8 V power supply.     

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.     

An alternative method for transistor low frequency noise estimation by measuring phase noise of test oscillator

In this paper we suggest an alternative method for the analysis of low frequency noise of transistors based on measurements of phase noise of a test oscillator. This method is demonstrated by experimental results obtained with a simple test oscillator with HEMT, and central frequency of 13.769 GHz. The main contribution to phase noise of the test oscillator comes from up conversion of transistor LF noise. This idea and the method can be used for the selection of transistors for high frequency application or for design of test circuit in RF IC manufacture.     

A 1-V 4-GHz wide tuning range voltage-controlled ring oscillator in 0.18 μm CMOS

A new differential delay cell with complementary current control to extend the control voltage range as well as the operation frequency is proposed for low voltage and wide tuning range voltage-controlled ring oscillator (VCRO). The complementary current control can get rid of the restriction that control voltage is unable to cover the full range of power supply voltage in a conventional VCRO. A three-stage VCRO chip working with 1 V power supply voltage is constructed using 0.18 μm 1P6M CMOS process for verifying the efficacy of the proposed differential delay cell. Measured results of the VCRO chip show that a wide range of operation frequency from 4.09 GHz to 479 MHz, a tuning range of 88%, is achieved for the full range of control voltage from 0 to 1 V. The power consumptions of the chip are 13 and 4 mW for oscillation outputs of 4.09 GHz and 479 MHz, respectively. The measured phase noise is −93.3 dBc/Hz at 1 MHz offset from 4.09 GHz center frequency. The core area of the chip is 106 μm×76.2 μm.     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

A low-power differential injection-locked frequency divider with output power flatness in 0.5 μm E/D-mode GaAs PHEMT

This study implemented an injection-locked frequency divider (ILFD) on Ka-band millimeter-wave communication systems in 0.5 μm enhancement/depletion-mode (E/D-mode) GaAs PHEMT technology. The ILFD presents a low-power design based on the differential-injection circuit topology without using any injectors. Compared with the conventional single-injection ILFD circuits, the proposed ILFD exhibits output power flatness and wide locking range characteristics with a power consumption of 0.9 mW under a 0.4 V supply. The self-oscillation frequency was chosen to be 20 GHz for divided-by-2 operation. The measured locking range is approximately 11.5 GHz ranging from 32.5 GHz to 44 GHz when the injection power level is 5 dBm. The locking range exhibiting a 3 dB power roll-off characteristic at output is 10.5 GHz ranging from 33 GHz to 42.5 GHz.     

A SiGe HBT low noise amplifier using on-chip notch filter for K band wireless communication

In this paper a new notch filter topology has firstly been described. In order to improve the input match as well as enhance the gain on the operating frequency of 20.5 GHz, extra capacitor has firstly been added in the passive base-collector notch filter forming a new scheme, eliminating the operating-frequency (op) input mismatch in formal base-collector notch filters. EM simulations have shown that the LNA obtained 14.1 dB gain at 20.5 GHz and high image-rejection ratio (IRR) of 33.5 dB at image frequency of 15 GHz, and S₁₁ of -15 dB was obtained compared to −8 dB without notch filter at operating frequency, NF was below 5 dB at gain peak frequency, power consumption was 18 mW at 3 V voltage supply, and IIP3 was 3.43 dBm ensuring a high linearity in SiGe bipolar process.     

New design of low power, 100 Mb-s IR-UWB pulse generator in 0.18 µm CMOS technology

A new method of impulse radio ultra-wideband (IR-UWB) pulse generation, with advantage of providing a “notch” like representation of pulse in the spectrum domain for particular control parameters values, is investigated in this paper. Low power pulse generator is composed of a glitch generator, a switched oscillator, a two-stage buffer and a pulse shaping filter. The proposed architecture, designed in UMC 0.18 µm CMOS technology, can operate in a single band from 3.3 GHz to 9.3 GHz or in a double, lower and higher UWB band (from 3 GHz to 9.15 GHz), suppressing frequencies in the WLAN band. Both spectrums fully comply with the corresponding FCC spectral mask, while the pulse generator regime and the spectrum range are determined by control signal values. Post-layout simulation results showed a pulse width of 0.5 ns, and a peak-to-peak amplitude of 211 mV for one band spectrum. The average power consumption is 0.89 mW corresponding to the energy consumption of 8.9 pJ/pulse for 100 MHz pulse repetition rate (PRF). The pulse duration is 1 ns and peak-to-peak amplitude is 202 mV in the case of the WLAN frequency band suppression. The total chip area is 0.31 mm². The pulse generator has been evaluated for the best performance supporting the on-off keying (OOK) modulation.     

Multiband BPF with wide upper stop band using asymmetrically positioned stub loaded open loop resonators

In this paper, asymmetrically positioned stub loaded open loop resonators with pseudo interdigital coupling are used to design compact multiband planar bandpass filters. The first design pertains to a dualband BPF that operates at 3.5 GHz and 5.7 GHz. The parameters like position of stub, which quantifies the asymmetry, and length of stub are further optimised using real coded genetic algorithm to evolve a triband BPF. The evolutionary design procedure is supported with an example of triband BPF having passband at 3.5 GHz, 5.5 GHz and 6.8 GHz, respectively. The transmission line models for both filters are developed as well as fabricated prototypes are realised and tested. There is a good agreement between the measured and simulated results. The measured insertion loss at first and second band centred around 3.5 GHz and 5.7 GHz of the dual band BPF are 1.5 dB and 1.25 dB, respectively. For the triband BPF the values are 1.24 dB, 1.6 dB and 1.8 dB at 3.5, 5.5 and 6.8 GHz, respectively. The dualband design covers the WiMAX and IEEE 802.11a bands where as the triband design also covers the 6.8 GHz RFID frequency.     

Design of ultra wideband trapezoidal shape slot antenna with circular polarization

A CPW-feed printed slot antenna with circular polarization characteristics is presented in this paper. The basic structure of the antenna is a rectangular slot excited by a 50 Ω CPW line terminated on a trapezoidal shaped tuning stub. Perturbations in the form of circular stubs are applied in the slot to realize circular polarization. The measured impedance bandwidth (S₁₁ < −10 dB) for the initial design is 4.4 GHz (from 2.2 GHz to 6.6 GHz) while the 3-dB axial ratio bandwidth is 1.77 GHz (from 4 GHz to 5.77 GHz) which is 36.23% at the center frequency of 4.88 GHz. The basic structure of the antenna was further modified to enhance the impedance bandwidth to reach well beyond 12 GHz while increasing the ARBW to 44.3% (from 4.3 GHz to 6.75 GHz). The proposed antenna in its final version has a measured peak gain of about 5 dB throughout the useful band and nearly stable radiation pattern.     

Wideband frequency and in situ characterization of aluminum nitride (AlN) in a metal/insulator/metal (MIM) configuration

This paper deals with the electrical wideband frequency and in situ characterization of aluminum nitride (AlN) material. This material is interesting for bulk acoustic wave (BAW) or surface acoustic wave (SAW) devices. In a first step, low frequency characterizations allow to know current versus voltage characteristics, leakages and temperature dependence of the electrical properties. Then, AlN properties in an integrated “metal/insulator/metal” configuration are characterized using MIM waveguide and RLCG parameters are measured up to 20 GHz. An electrical field breakdown of 7.5 MV cm⁻¹ and a relative permittivity between 9 and 10 are extracted. Acoustic resonances, validated with Mason one-dimensional simulation, occur near 5 and 12 GHz. Finally, the MIM devices performances are determined in a wideband frequency: from 1 MHz to 10 GHz.     

New implementation of injection locked technique and its application to low phase noise quadrature oscillators

A new implementation of the injection locked technique is proposed. The incident signal is directly injected into the common-source connection node of the sub-harmonic oscillator instead of the gate of the tail current source, and a narrowband noise filtering network is inserted into the same node to suppress the tail current source noise. A novel quadrature oscillator with the proposed injection locked technique is presented. The simulations show that the phase noise of the quadrature oscillator is about 7 dB better than that of the stand-alone sub-harmonic oscillator. The quadrature oscillator has been implemented in 0.25 um CMOS process and the measured results show that the proposed quadrature oscillator could achieve a phase noise of −130 dBc/Hz at 1 MHz offset from 1.13 GHz carrier while only drawing an 8.0 mA current from the 2.5 V power supply.     

Design of 20 GHz high performance LC-VCOs in a 52 GHz fT SiGe:C BiCMOS technology

The design and analysis of fully integrated 20 GHz voltage controlled oscillators (VCOs) for low cost and low power communication system are presented in this paper. Two differential topographies have been studied: balanced Colpitts VCO and LC-VCO using a cross-coupled differential pair. We have focused on oscillation frequency, tuning range, phase noise, output power optimization and buffer stage specifications. SiGe:C hetero-junction bipolar transistors of a 52 GHz cut-off frequency have been used and produced via a monolithic BiCMOS technology.