高K栅堆叠结构MOSFET器件阈值电压不稳定度的半经验解析模型

A semi-empirical analytic model for the threshold voltage instability of MOSFET is derived from the Shockley-Read-Hall (SRH) statistics in this paper to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression of the filled trap density in terms of the dynamic time is derived from the SRH statistics. The semi-empirical analytic model of the threshold voltage instability is developed based on the MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by the extensive experimental data of the trapping and de-trapping stress from the different high k gate configuration.     

A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks

n the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations.     

A 2D sub-threshold current model for single halo triple material surrounding gate (SHTMSG) MOSFETs

In the proposed work analytical modeling of single halo triple material surrounding gate (SH-TMSG) MOSFET is developed. The threshold voltage and subthreshold current has been derived using parabolic approximation method and the simulation results are analyzed. The threshold voltage roll off is reduced and it denotes the deterioration of short channel effects. The results of the analytical model are delineated and compared with MEDICI simulation results and it is well corroborated.     

A continuous semi-empiric transfer characteristics model for surrounding gate undoped polysilicon nanowire MOSFETs

A new continuous semi-empiric compact model for the current transfer characteristics of surrounding gate undoped polycrystalline silicon (Poly-Si) nanowire (NW) MOSFETs is proposed. The model consists of a single equation based on the Lambert function, which contains only four parameters and is continuously valid and fully differentiable throughout weak and strong conduction regimes of operation. The model is tested on measured transfer characteristics of experimental devices. The extracted model parameters are used to generate transfer characteristics playbacks that are then compared to the measured data to validate the proposed model’s adequacy for these devices.     

Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator(DMG SSOI) MOSFETs is developed.We investigate the improved short channel effect(SCE),hot carrier effect(HCE),drain-induced barrier-lowering(DIBL) and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain ...     

异质栅全耗尽型应变硅 SOI MOSFET二维解析模型*

本文首次并建立了异质栅全耗尽型应变Si SOI (DMG SSOI) MOSFET的二维表面势沿沟道变化的模型．并对该结构的MOSFET的短沟道效应SCE (short channel effect),热载流子效应HCE(hot carrier effect),漏致势垒降低DIBL (drain induced barrier lowering)和载流子传输效率进行了研究．该模型中考虑以下参数：金属栅长,金属栅的功函数,漏电压和Ge在驰豫SiGe中的摩尔组分．结果表明沟道区的表面势引进了阶梯分布,正是这个阶梯分布的表面势抑制了SCE,HCE和DIBL．同时,应变硅和SOI(silicon-on-insulator)结构都能提高载流子的传输效率,特别是应变硅能提高载流子的传输效率．此外阈值电压模型能者正确表明阈值电压随栅长比率L2/L1减小或应变Si膜中Ge摩尔组分的降低而升高．数值模拟器ISE验证了该模型的正确性．     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。     

An accurate two-dimensional CAD-oriented model of retrograde doped MOSFETs for improved short channel performance

An analytical CAD-oriented model for short channel threshold voltage of retrograde doped MOSFETs is developed. The model is extended to evaluate the drain induced barrier lowering parameter (R) and gradient of threshold voltage. The dependence of short channel threshold voltage and R on thickness of lightly doped layer (d) has also been analyzed in detail. It is shown that a retrograde doping profile reduces short channel effects to a considerable extent. A technique is developed to optimize the device parameters for minimizing short channel effects. The results so obtained are in close proximity with published data.     

New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs

Using an exact solution of two-dimensional Poisson’s equation in cylindrical coordinates,a new analytical model comprising electrostatic potential,electric field,threshold voltage and subthreshold current for halodoped surrounding-gate MOSFETs is developed.It is found that a new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of the silicon channel is much larger than that of the oxide.It is also revealed that moderate halo doping concentration,thin gate oxide thickness and small silicon channel radius are needed to improve the threshold voltage characteristics.The derived analytical model agrees well with a three-dimensional numerical device simulator ISE.     

Analytical threshold voltage and subthreshold swing model for TMG FinFET

An analytical modelling of the subthreshold surface potential, threshold voltage (V_T) and subthreshold swing (SS) for a triple material gate (TMG) FinFET is presented. The basis of the 3D solution is two separate 2D solutions. The FinFET is separated into two 2D structures: asymmetric triple material double gate (TMDG) and symmetric TMDG MOSFETs. Their potential distributions are obtained by solving the corresponding 2D Poisson’s equations. The potential distribution in TMG FinFET is obtained by a parameter-weighted sum of the two 2D solutions. Utilising the concept of minimum source barrier as the leakiest channel path, the minimum value of the surface potential is developed from the potential model. This leads to the derivations for the threshold voltage and SS. Furthermore, the effects of variation in gate work function and gate length are investigated for analytically developed SS and V_T models. Our models are validated against TCAD Sentaurus-simulated results and found to be quite accurate.     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

Analytical 2D modeling for potential distribution and threshold voltage of the short channel fully depleted cylindrical/surrounding gate MOSFET

A two-dimensional analytical model for fully depleted cylindrical/surrounding gate MOSFET is presented. We used the evanescent mode analysis to solve the 2D Poisson's equation and to deduce analytically the surface potential and threshold voltage expressions of this device. Comparison with the other models reveals a good agreement.     

Modeling of threshold voltage of a quadruple gate transistor

In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. For numerical simulation, self-consistent Schrodinger-Poisson equations, calibrated by 2D non equilibrium green function simulation, are used. This analytical model not only provides useful physics insight of effects of gate length and body width on the threshold voltage, but also serves as a basis for compact modeling of quadruple gate MOSFETs.     

Two-dimensional threshold voltage analytical modes of DMG strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further,the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.     

Analytical model for the high-temperature behaviour of the subthreshold slope in MuGFETs

As MuGFETs are promising contenders for the end of the silicon Roadmap, their high-temperature behaviour needs to be addressed. In this work we investigate the variations of the subthreshold slope (SS) of double-gate devices and MuGFETs with intrinsic doping as a function of the temperature and fin width. Focus is placed on the superlinear behaviour of SS occurring above a certain temperature threshold. Numerical simulations are performed using Comsol Multiphysics^™ and a 1D analytical model is developed. The model, which includes the effect of film and gate oxide thickness, is shown to accurately fit the numerical data. A new definition for the subthreshold slope under high-temperature operation is proposed. The high-temperature subthreshold slope degradation is shown to increase with fin width.     

An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs

An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Two-dimensional Poisson equation is solved analytically using series method and channel potential is obtained. The analytical expression for subthreshold swing is achieved. Model results are compared with Medici simulation results, both of them turn out to agree very well. The results show the variation of channel potential and subthreshold swing with channel length, gate bias, and oxide thickness, which will provide some guidance for the integrated circuit designs.     

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.     

Electric potential and threshold voltage models for double-gate Schottky-barrier source/drain MOSFETs

The threshold voltage, V_th of a double-gate (DG) Schottky-barrier (SB) source/drain (S/D) metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. An analytic expression for surface potential is obtained by using Gauss's law and solving Poisson's equation, the results of which are compared with simulations, and good agreement is observed. Based on the potential model, a new definition for V_th is developed, and an analytic expression for V_th is obtained, including quantum mechanical effects and SB lowering effect. We find that V_th is very sensitive to the silicon body thickness, t_si. For a device with a small t_si (<3 nm), V_th increases dramatically with the reduction of t_si. V_th decreases with the increase of the back-gate oxide thickness, and with the increasing of the drain bias. All the results can be of great help to the ultra-large scale integrated-circuit (ULSI) designers.     

Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon-germanium substrates

The present work gives some insight into the subthreshold behaviour of short-channel double-material-gate strained-silicon on silicon-germanium MOSFETs in terms of subthreshold swing and off-current. The formulation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLAS^TM by Silvaco Inc.     

An accurate, analytical, and technology-mapped definition of the surface potential at threshold and a new postulate for the threshold voltage of MOSFETs

A novel approach of defining the threshold voltage for long channel MOSFETs has been presented in this paper, where it has been proposed that it corresponds to the gate-to-source voltage for which the drift and diffusion components of the total drain current become equal to each other. In order to avoid the greater computation time associated with the numerical solution of these two components, an analytical expression of the surface potential, corresponding to the threshold condition, is given here, which has the same functional form as the one proposed by Tsividis. The fuzzy parameter n, appearing in this expression of the surface potential, is expressed as a function of the substrate doping density (N_A) and the oxide thickness (t_ox). The threshold voltage values, obtained analytically from the relation between the surface potential at the threshold condition and the closed-form technology-mapped expression of the fuzzy parameter n, show an excellent match with those obtained from SILVACO simulations for a wide range of N_A and t_ox, with the maximum error being only about 4%. The comparison of the percent error values of the threshold voltage obtained from this proposed model with those obtained from the other two recently proposed methods, all with respect to SILVACO simulation results, further verifies the validity of our completely analytical, mathematically simple, and straight-forward approach, proposed in this work here.