一个电容阵列定制的100MS/s，9bit，0.43mW逐次逼近型模数转换器

本论文介绍了一个带定制电容阵列的低功耗9bit,100MS/s逐次比较型模数转换器。其电容阵列的基本电容单元是一个新型3D,电容值为1fF的MOM电容。除此之外,改进后的电容阵列结构和开关转换方式也降低了不少功耗。为了验证设计的有效性,该比较器在TSMC IP9M 65nm LP CMOS工艺下流片。测试结果如下：采样频率100MS/s,输入频率1MS/s时,有效位数（ENOB）为7.4,bit,信噪失真比（SNDR）为46.40dB,无杂散动态范围（SFDR）为62.31dB。整个芯片核面积为0.030mm2,在1.2V电源电压下功耗为0.43mW。该设计的品质因数（FOM）为23.75fJ/conv。     

An ultra low-power DAC with fixed output common mode voltage

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V_cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 μm technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC.     

A self-calibration method for capacitance mismatch in SAR ADC with split-capacitor DAC

A self-calibration method to calibrate the nonlinearity due to capacitance mismatch in successive approximation register (SAR) analog-to-digital converter (ADC) is presented. It focuses on calibrating the most significant bit (MSB) array in the split-capacitor main DAC (split-MDAC) by using a calibration DAC (CDAC) that contains multiple sub-CDACs. Every bit in MSB array has its corresponding sub-CDAC in CDAC, which enhances the calibration efficiency. To verify the calibration method, a 14 bit, 500 kS/s SAR ADC is implemented, and it is manufactured in 0.35 μm 2P4M CMOS process. The measured results show that the proposed calibration method can assist this SAR ADC to achieve better static and dynamic performance, and its ENOB is improved from 9 bit to 11.98 bit at Nyquist input frequency.     

低DNL的SAR型模数转换器的设计

保证DAC中元器件的精度、减小DNL误差是提高SAR ADC性能的关键。通过对SAR ADC内部DAC的结构进行综合分析,针对传统的C-R混合式结构中的集总电容阵列进行了优化设计。电容阵列由相同的非集总的单位电容组成,并通过数字逻辑的控制来实现对单位电容连接点的选择。验证结果证明设计有效,ENOB、SFDR和SINAD等参数都得到明显的提高,保证了SARADC的单调性,实现了低DNL的SAR型模数转换器的设计。     

低功耗10位100MHz流水线A/D转换器设计

介绍了一个10位100 MHz,1.8 V的流水线结构模/数转换器（ADC）,该ADC运用相邻级运算放大器共享技术和逐级电容缩减技术,可以大大减小芯片的功耗和面积。电路采用级联1个高性能前置采样保持单元和4个运放共享的1.5位/级MDAC,并采用栅压自举开关和动态比较器来缩减功耗。结果显示,在输入频率达到奈奎斯特频率范围内,整个ADC的有效位数始终高于9位。电路使用TSMC 0.18μm 1P6 M CMOS工艺,在100 MHz的采样频率下,功耗仅为45 mW。     

一种基于新型低功耗开关策略的10 bit 120 MS/s SAR ADC

设计了一种10 bit 120 MS/s高速低功耗逐次逼近模数转换器(SAR ADC)。针对功耗占比最大的CDAC模块,基于电容分裂技术并结合C-2C结构,提出了一种输出共模保持不变的双电平高能效开关控制策略;在降低CDAC开关功耗的同时,摆脱了CDAC开关过程中对中间共模电平的依赖,使得该结构适用于低电压工艺。在速度提升方面,控制逻辑使用异步逻辑进行加速;比较器采用一种全动态高速结构,在保证精度的前提下其工作频率达到3 GHz; CDAC中插入冗余位,以降低高位电容对充电时间的要求。所设计的SAR ADC使用40 nm CMOS工艺实现,采用1.1 V低电压供电。在不同工艺角下进行性能仿真,结果显示,在120 MHz采样率下,有效位数为9.86 bit,无杂散动态范围为72 dB,功耗为2.1 mW,优值为18.9 fJ/(conv·step)。     

Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC)

A foreground calibration technique of a pipeline analog-to-digital converter (ADC) has been presented in this paper. This work puts an emphasis on erroneous ADC output occurring due to device mismatch, which, in any standard CMOS process boils down to capacitor mismatch. Deviation of gain of a multiplying digital-to-analog converter (MDAC), also known as the radix of a pipeline ADC stage, from its ideal values adds to the non-linearity of the ADC output. Capacitor mismatch is a major contributor for such an error. The proposed foreground calibration technique makes use of a simple arithmetic unit to extract the radix value from the ADC output for calibration. It uses a sinusoidal signal at the input for calibration purposes. The input sinusoidal signal can be sampled by the ADC clock at any rate for the calibration algorithm to be successful. Behavioral simulation of a pipeline ADC with 5% capacitor mismatch supports the established technique. To verify the calibration algorithm further, pipeline ADCs of different resolutions have been designed and simulated in a 0.18 μm CMOS process.     

SAR A/D转换器中电容失配问题的分析

在逐次逼近型(SAR)A/D转换器的设计过程中,电容网络的匹配精度对A/D转换器系统精度有着至关重要的影响。详细推导了电容失配误差与A/D转换器精度的关系表达式,给出了严密的理论证明,为电路设计人员选择工艺、版图方式、电路结构和电容大小提供了有力的理论基础。此论证方式也适用于电阻网络等其他二进制加权网络的精度计算。     

Passive reference-sharing SAR ADC

Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used for their simple architecture, inherent low-power consumption and small footprint. Several techniques aiming to reduce the power consumption, to increase the speed, and to reduce the capacitance spread have been developed, such as splitting the digital-to-analog converter (DAC) capacitor array, and charging and discharging the DAC capacitors in multiple steps. In this paper, a fully differential, low-power, passive reference voltage sharing SAR ADC architecture is presented, along with its theoretical analysis and test results. In this architecture, suitable for low sampling rate and low-resolution applications, the reference voltage is scaled down by successively connecting equally sized capacitors in parallel, allowing the use of small capacitor for its implementation. The implemented 6-bit ADC is one of the smallest ADCs reported in a 180-nm technology, and features a FoM between 30.8 and 39.3 fJ per conversion step without considering the clock generator power consumption.     

基于分段电容阵列的改进型逐次逼近型ADC

为缩短高速模数转换器(ADC)中高位(MSB)电容建立时间以及减小功耗,提出了一种基于分段式电容阵列的改进型逐次逼近型(SAR)ADC结构,通过翻转小电容阵列代替翻转大电容阵列以产生高位数字码,并利用180 nm CMOS工艺实现和验证了此ADC结构。该结构一方面可以缩短产生高位数码字过程中的转换时间,提高量化速度;另一方面其可以延长大电容的稳定时间,减小参考电压的负载。通过缩小比较器输入对管的面积以减小寄生电容带来的误差,提升高位数字码的准确度。同时,利用一次性校准技术减小比较器的失配电压。最终,采用180 nm CMOS工艺实现该10 bit SAR ADC,以验证该改进型结构。结果表明,在1.8 V电源电压、780μW功耗、有电路噪声和电容失配情况下,该改进型SAR ADC得到了58.0 dB的信噪失真比(SNDR)。     

高速高精度SAR ADC电容电压系数校正

基于XFAB工艺参数,设计了一种不受电容电压系数影响的高速高精度SAR ADC。在理论上定性分析了电容电压系数对高速高精度SAR ADC的影响,并使用Matlab进行定量分析。分析结果表明,1阶与2阶电容电压系数对ADC性能的影响具有不同的特点。针对1阶电容电压系数,使用改进的分裂电容结构进行消除;针对2阶电容电压系数,使用分段数字补偿来进行校正。校正完成以后,电容电压系数引起的非线性误差可以从±11.7 LSB降到±0.5 LSB以下,无杂散动态范围可以提高10 dB以上。     

High-speed single-channel SAR ADC with a novel control logic in 65 nm CMOS

This paper presents an 8-bit 320 MS/s single-channel successive approximation register (SAR) analog-to-digital converter (ADC) with low power consumption. Through a procedure of splitting all the most significant bit (MSB) capacitors except the least significant bit (LSB) capacitor into two equal sub-capacitors and reusing the terminal capacitor, the average switching energy and total capacitance can be reduced by about 87 and 50% respectively compared to the conventional procedure. Meanwhile, high-speed operation can be achieved by using a novel SAR control logic featuring efficient hardware cost and small critical path delay. In addition, this paper analyzes how to obtain the value of the unit capacitance which exhibits trade-offs between conversion rate, power consumption and linearity performance. The SAR ADC is simulated in 65 nm CMOS technology. It can achieve 48.63 dB SNDR, 63.61 dB SFDR at a supply voltage of 1.2 V and sampling frequency of 320 MS/s for near-Nyquist input, consuming 2.59 mW of power and with a FoM of 37 fJ/conversion-step.     

A 12-bit 250 MS/s pipeline ADC with 78 dB SFDR in 0.13-µm CMOS

A 12-bit 250 MS/s pipeline ADC is presented and implemented in 0.13 µm CMOS process. To reduce the load capacitance of each pipeline stage and save area, the inter-metal capacitors are adopted as input sampling capacitors of the comparators. A fully integrated reference buffer associated with a simulation scheme is proposed to improve the settling speed and PSRR of the differential reference voltage. To reduce the overall power a low cost foreground calibration for capacitor mismatches is employed. The single-stage telescopic with gain-boosting amplifiers and an improved bias is applied in each stage due to its high power efficiency. Additionally, the timing in the sampling phase is optimised to achieve high sampling linearity. Even harmonics induced by parasitic capacitance are analysed profoundly and mitigated at the level of layout. The measured SNDR and SFDR are 63 and 78 dB with 38.1 MHz input, respectively, and remain 63 and 77 dB with Nyquist input. The ADC core area is 1.6 mm² and consumes 165 mW (reference buffer included, LVDS excluded) at 250 MS/s under 1.3 V.     

一个采用面向建立走线优化的定制三维1-fF MOM单位电容的电容型数模转换器

异步逐次比较模数转换器由于其高能效和中高性能在近年来得到了广泛的关注。其设计性能的主要瓶颈在于其单位电容的大小。本文提出了一种三维结构的金属-氧化层-金属电容,其单位电容大小仅为1 fF。该电容形似伞状,以此实现快速建立的性能需求。作者将该电容和目前国际顶尖的定制化三维电容结构进行了比较。为了验证该电容的有效性,作者设计了一个基于该电容的6位电容型数模转换器,基于TSMC 1P9M 65nm LP CMOS工艺。该数模转换器在100MS/s的工作速度下功耗为0.5mW,其中没有包含以可测性为目的的源级跟随器。静态性能测试结果显示该数模转换器的INL小于 /- 1LSB,DNL 小于 /- 0.5 LSB,从而证明了该电容的有效性。     

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380 μm².     

一种应用于流水线ADC的自适应后台校正技术

流水线模数转换器(Pipeline ADC)是一种应用广泛的模数转换器结构,可以同时实现高速和高精度性能。然而电路的非理想性严重制约着流水线ADC的性能。提出了一种自适应数字技术,通过使用低速但准确的ADC作为基准,与待校正的流水线ADC并联,并将两者的数字输出的差值送入数字自适应滤波器中进行处理,使流水线ADC的输出不断逼近低速但准确的ADC输出,从而达到数字校正的目的。仿真结果表明,这种方法可以有效去除包括电容失配、有限运放增益、运放失调在内的误差。     

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB

This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.     

A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction

A low power 10-bit 250-k sample per second(KSPS) cyclic analog to digital converter(ADC) is presented. The ADC’s offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence.The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator’s offset errors and switched capacitor mismatch errors.With this structure,it has the advantages of simple circuit configuration,small chip area and low power dissipation.The cyclic ADC manufactured with the Chartered 0.35μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate.It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42×0.68 mm~2.     

基于流水线ADC的MDAC电容失配校准研究

针对MDAC中采样电容失配会降低ADC输出非线性性能的问题,提出了一种流水线ADC的前台数字校准技术。该前台数字校准技术利用ADC输出积分非线性的相对偏差提取误差,利用简单的多路选择运算单元进行误差补偿。在此基础上,采用Verilog HDL实现了RTL级描述并成功流片。仿真和测试结果表明,该校准算法能够提升ADC输出性能。     

一种用于16位流水线ADC的多比特子DAC电容失配校准方法

多比特子DAC的电容失配误差在流水线AIX:输出中引入非线性误差,不仅严重降低AEK、转换精腰.而且通常的校准技术无法对非线性误差进行校准.针对这种情况,本文提出了一种用于16位流水线ADC的多比特子DAC电容失配校准方法.该设计误差提取方案在流片后测试得到电容失配误差.进而计算不同输入情况下电容失配导致的MDAC输出误差,根据后级的误差补偿电路将误差转换为卡乏准码并存储在芯片中,对电容失配导致的流水级输出误差进行校准.仿真结果表明.卡《准后信噪失真比SINAD为93.34 dB.无杂散动态范围SFDR为117.86 dB,有效精度EN()B从12.63 bit提高到15.26 bit.