Vertical nanowire/nanosheet FETs with a horizontal channel for threshold voltage modulation

A new type of vertical nanowire(VNW)/nanosheet(VNS)FETs combining a horizontal channel(HC)with bulk/back-gate electrode configuration,including Bulk-HC and FD-SOI-HC VNWFET,is proposed and investigated by TCAD simulation.Comparisons were carried out between conventional VNWFET and the proposed devices.FD-SOI-HC VNWFET exhibits better Ion/Ioff ratio and DIBL than Bulk-HC VNWFET.The impact of channel doping and geometric parameters on the electrical character-istic and body factor(γ)of the devices was investigated.Moreover,threshold voltage modulation by bulk/back-gate bias was im-plemented and a largeγis achieved for wide range V_thmodulation.In addition,results of I_onenhancement and Ioff reduction in-dicate the proposed devices are promising candidates for performance and power optimization of NW/NS circuits by adopting dynamic threshold voltage management.The results of preliminary experimental data are discussed as well.     

Development of a 10-kV regional compensation dynamic voltage restorer with multiple functions

The first 10-kV regional compensation dynamic voltage restorer (DVR) has been installed in a 110-kV substation in Shenzhen power grid, to protect plenty of sensitive loads in a wide area simultaneously from the disturbances caused by voltage sags. The location selection and performance indicators of the DVR are determined based on the voltage sag statistic results in recent years of Shenzhen power grid. The implementation schemes of main circuit elements, such as the energy storage unit, inverter and LC filter are presented. To further improve the DVR’s cost-effectiveness, a novel virtual impedance control strategy is proposed to provide the DVR with a function of a Fault Current Limiter (FCL) or a Series Compensator (SC) besides the function of voltage sag compensation. Simulation and field experimental results are provided to show the correctness and effectiveness of the main circuit design and control system development of the 10-kV DVR.     

A low power current-reuse LC-VCO with an adaptive body-biasing technique

This work presents a low-power low-phase noise current-reuse LC voltage controlled oscillator (VCO) with an adaptive body-biasing technique that enhances the reliability of the proposed circuit under process, voltage, and temperature (PVT) variations. Furthermore, the supply voltage and power consumption of the proposed VCO are reduced by the start-up oscillation condition that is provided by the adaptive body-biased circuit. This property is in fact very interesting from the power management perspective. The proposed VCO works at carrier frequency of 1.8 GHz and draws the power of only 306 µW from a 0.9 V supply. It achieves phase noise of −123.36 dBc/Hz at 1 MHz offset and provides a figure-of-merit (FoM) of −193.61 dBc/Hz. The post-layout simulation results of designed VCO in 0.18 µm standard CMOS technology confirm the effectiveness of the proposed circuit.     

High efficiency boost converter with variable output voltage using a self-reference comparator

This paper presents a boost converter with variable output voltage and a new maximum power point tracking (MPPT) scheme for biomedical applications. The variable output voltage feature facilitates its usage in a wide range of applications. This is achieved by means of a new low-power self-reference comparator. A new modified MPPT scheme is proposed which improves the efficiency by 10%. Also, to further increase the efficiency, a level converter circuit is used to lower the V_dd of the digital section. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. Using this approach, a thermoelectric energy harvesting circuit has been designed in a 180 nm CMOS technology. According to HSPICE Simulation results, the circuit operates from input voltages as low as 40 mV and generates output voltages ranging from 1 to 3 V. A maximum power of 138 μW can be obtained from the output of the boost converter which means that the maximum end-to-end efficiency is 52%.     

A 1 V CMOS programmable accurate charge pump with wide output voltage range

A 1 V, programmable, accurate, high speed, single-ended charge pump is proposed, suitable for low voltage PLLs. It is designed in TSMC 90-nm digital CMOS process and it consists of four switches in a current steering configuration, a unity gain rail to rail buffer for the charge sharing effect elimination, one more rail to rail amplifier for minimizing the DC current mismatch, a programmable current bias circuitry and two drivers based on the standard cell XOR gates specific configuration for achieving good synchronization between all charge pump input pulses at the PLL lock state. Replica biasing technique is applied to all charge pump switches. Current glitches and charge mismatch are suppressed by employing a mechanism with additional switches at the output. It exhibits a maximum DC current mismatch of 1% and charge mismatch of 6% over a wide output voltage range of 0.7 V for the entire range of output currents. The wide range of the output voltage remains relatively constant and independent of the selected charge pump current amplitude. This is attained by applying appropriate variation of the W/L ratios of the bias cascode current sources via the employment of additional programmable switches such that their saturation voltages remain relatively constant, something which in turn enables the output currents range to be as wide as it is required.