基于改进忆阻器的高通滤波器设计与仿真

针对传统的忆阻器模型存在不能很好地与HP实验室提出的忆阻器物理模型中忆阻器的阻值变化特点相符的问题,提出了一种改进的带有阈值电压的忆阻器模型,该模型能很好地模拟忆阻器的"激活"现象,其特性与HP实验室的忆阻器物理模型相符;基于该改进模型设计了一种高通滤波器电路,该电路通过改变忆阻器阻值控制电路的输出信号来改变忆阻器的阻值,从而实现了滤波器截止频率的调节。SPICE仿真结果验证了设计的正确性。     

忆阻器的温度效应改进模型及其仿生神经突触传递

突触传递是温度敏感的,由于缺乏温度依赖性的突触电导分析模型,无法在神经系统建模时包括温度效应.忆阻器因其阻值连续可变和纳米尺寸的优势,被广泛认为可以模拟生物突触.本文通过改进忆阻保留值和考虑温度对离子迁移和扩散的影响,提出一种新的氧化钨忆阻器模型,此模型更加符合忆阻器的实际行为特性.首先,改进的数学模型不仅具有原模型的功能,同时可以拟合忆阻器的实际遗忘规律.另外,将此忆阻器作为生物突触耦合两个相同的HH神经元,能够体现温度对突触传递的影响,即温度上升引起氧空位迁移和扩散速率发生变化,导致忆阻器电导变化速率加快,进一步影响兴奋性突触后膜电位幅值和放电次数,而相关仿真结果与神经生理实验现象相符.本文的工作表明,改进的氧化钨忆阻器模型更适合作为仿生突触应用到神经形态系统中,将为指导忆阻器的设计制造工艺以提高其仿生突触性能提供参考,也为研究温度对突触传递的影响提供了一种新思路.     

忆阻器交叉阵列及在图像处理中的应用

忆阻器是一种有记忆功能的非线性电阻,其阻值的变化依赖于流过它的电荷数量或磁通量.忆阻器作为第4个基本的电路元件,在众多领域中有巨大的应用潜力,有望推动整个电路理论的变革.文中利用数值仿真和电路建模,分析了忆阻器的理论基础和特性,提出了一种用于图像存储的忆阻器交叉阵列,可以实现黑白、灰度和彩色图像的存储和输出,一系列的计...     

基于MNIST的忆阻神经网络稳定性研究

为了探究忆阻器的稳定性问题对忆阻神经网络性能的影响,基于等效电阻拓扑结构的忆阻器模型,搭建了一个将忆阻器作为突触的BP神经网络,并利用MNIST数据集对该网络进行训练和测试。忆阻器的稳定性问题通过设置忆阻器参数波动来模拟,最终发现忆阻器一定程度内的性能波动会促进神经网络的收敛,但波动过大则会降低网络的收敛速度。为了表征波动的临界程度,测得了基于忆阻器模型的各参数的最大波动范围,并进一步计算出忆阻器件工艺层次参量的取值范围,为忆阻神经网络硬件化中忆阻器件的工艺制造和选用提供了参考。     

忆阻器状态逻辑中与操作的高效设计与实现

作为电阻、电容、电感之外的第4种基本电路元件,忆阻器自2008年被发现以来受到学术界和产业界的广泛关注.忆阻器的阻值记忆效应和纳米工艺制造方式使其被认为可用于构建未来更大容量和密度的存储器,逐渐替代FLASH等现有存储器件.除存储功能外,HP公司在2010年《Nature》上发表的文章表明,忆阻器还可以通过以蕴含为基础的状态逻辑实现任意逻辑运算.研究了忆阻器状态逻辑的另一种操作——与操作,提出了一种更加高效的与操作实现方法,该方法不需要增加额外的忆阻器,降低了激励电压的复杂性,减小了误差,使运算更加简便高效.最后通过SPICE模拟仿真对提出的方法进行了验证.     

忆阻桥放大效应在光纤式结冰探测中的应用

鉴于双光路通道差动测量方法能够有效去除共模干扰,本文将新型电路元件—忆阻器与传统的光纤式结冰传感器相结合,提出了纳米级尺寸具有放大效应的忆阻桥网络结构,分析了忆阻桥的放大效应原理,实现了光电二极管光电流信号的放大,以桥臂忆阻阻值和感知忆阻两端电压作为传感输出,对冰层厚度进行探测。仿真实验结果表明：该双测量通道忆阻桥网络结构能够同时有效消除光路扰动和扩大结冰厚度的测量范围。     

真实忆阻器数学建模以及电学仿真

忆阻器作为新一代的记忆设备,相比于传统的COMS具有低功耗,不挥发性,高集成密度等优良特性。本文提出了一种基于具体物理实验数据的忆阻器数学模型,实现了模拟过程能够最为接近真实忆阻基本特性。我们的模型符合忆阻器的随频率变化的三个基本特性,且具有浮点计算,双通道等优良的特征。分析比较了本文建立忆阻器和传统忆阻器的性能差异,并相对于数学模型给出仿真,仿真结果说明了此类忆阻器建立更适应于真实突触的仿真,可以有效的应用基于忆阻器的神经网络。     

基于忆阻器的连续学习混沌神经网络

忆阻器具有独特的记忆功能和连续可变的电导状态,在人工智能与神经网络等研究领域具有巨大的应用优势.详细推导了忆阻器的电荷控制模型,将纳米忆阻器与具有智能信息处理能力的混沌神经网络相结合,提出了一种新型的基于忆阻器的连续学习混沌神经网络模型.利用忆阻器可直接实现网络中繁多的反馈与迭代,即完成外部输入对神经元及神经元之间相互作用的时空总和.提出的忆阻连续学习混沌神经网络可以实现对已知模式和未知模式的区分,并能对未知模式进行自动学习和记忆.给出的计算机仿真验证了方案的可行性.由于忆阻器具有纳米级尺寸和自动的记忆能力,该方案有望大大简化混沌神经网络结构.     

基于阈值自适应忆阻器Hopfield神经网络的关联规则挖掘算法

针对基于Hopfield神经网络的最大频繁项集挖掘（HNNMFI）算法存在的挖掘结果不准确的问题,提出基于电流阈值自适应忆阻器（TEAM）模型的Hopfield神经网络的改进关联规则挖掘算法。首先,使用TEAM模型设计实现突触,利用阈值忆阻器的忆阻值随方波电压连续变化的能力来设定和更新突触权值,自适应关联规则挖掘算法的输入。其次,改进原算法的能量函数以对齐标准能量函数,并用忆阻值表示权值,放大权值和偏置。最后,设计由最大频繁项集生成关联规则的算法。使用10组大小在30以内的随机事务集进行1000次仿真实验,实验结果表明,与HNNMFI算法相比,所提算法在关联挖掘结果准确率上提高33.9个百分点以上,说明忆阻器能够有效提高Hopfield神经网络在关联规则挖掘中的结果准确率。     

一种基于荷控忆阻器的混沌电路

在原有忆阻器的定义上采用一种相对简单的荷控忆阻器模型,其忆阻M与电荷q的关系可以用一条二次曲线来描述。经仿真分析,其伏安特性曲线是一条类斜"8"字滞后回线,且会随着周期双极性输入信号的频率和振幅的变化而变化,并在一定程度上受到忆阻器本身参数的影响。用此荷控忆阻器代替蔡氏电路中的蔡氏二极管,得到含荷控忆阻器的电路,给出相轨图、Lyapunov指数与维数来验证其在一定参数配置下处于混沌状态。通过变换系统的初始值,验证了此混沌系统的运动轨迹在初始值微小的变化下会发生很大的差异。Lyapunov指数谱表明含荷控忆阻器的混沌系统在初始值变化时能够进入超混沌状态。利用劳斯判据判别了排除零特征根的影响下该混沌系统在平衡点处的稳定性。     

Development of a methodology for the extraction of BSIM3v3.2.2 parameters of Ge-channel MOSFETs and estimation of analog circuit performance

We have developed an algorithm which utilizes model equations for MOSFETs to extract BSIM3v3.2.2 MOSFET model parameters of Ge-channel transistors. The model represents the entire transfer characteristics from sub-threshold to strong inversion regions and the output characteristics from linear to saturation regions thus capturing all the operating bias conditions of gate to source voltage V_GS and drain to source voltage V_DS. For extraction of various BSIM parameters, the model equations are fitted with reported experimental characteristics, and some with TCAD simulation data of Ge MOSFETs for various geometrical dimensions over a wide range of bias conditions. The algorithm used for extracting BSIM3V3.2.2 parameters by fitting BSIM3v3.2.2 model equations with experimental or simulation data is written in MATLAB code. The extracted BSIM model parameters are employed in ADS circuit simulator to reproduce the transfer characteristics of Ge MOSFETs with the same channel length and channel width of 80 nm for both high and low body bias conditions. The characteristics obtained from ADS match well with those obtained from TCAD simulation using SILVACOATLAS thereby ensuring the accuracy of our extraction methodology. The extracted set of BSIM3V3.2.2 parameters is used to generate transfer and output characteristics of Ge channel pMOSFETs at channel length of 70 nm. The extracted value of threshold voltage, bulk mobility and saturation velocity are −0.2 V, 0.18 m²/V.s and 1.2 × 10⁶ m/s, respectively. Our study reveals that various device parameters such as transconductance, intrinsic voltage gain, and cut-off frequency show a maximum value of 677 μS/μm, 2.7, and 63 GHz, respectively.

     

双梁磁力压电振动能量采集器的实验和仿真

基于非线性技术改善能量采集器的能量采集效果作用,本文研究了非线性磁力耦合的双悬臂梁压电振动能量采集器,该采集器由两条不同的固有频率悬臂梁与永磁体组成.本文给出双梁磁力耦合压电能量采集器模型并建立了动力学方程式,通过实验测试获取相关参数与拟合磁力公式,数值仿真分析了双梁固有频率比1∶1.2与1∶1.5和永磁体初始间距40mm与30mm的4种结构能量采集器的电压输出性能与频率特征.根据数值分析设计实验:外激励加速度3m/s2作用下,双梁磁力结构能量采集器比单梁线性结构多一个电压共振峰;双梁固有频率比为1∶1.5比双梁固有频率比1∶1.2的电压响应带宽宽;初始磁距30mm共振峰值分别为(12Hz,39.4V)与(18Hz,13.4V)比初始磁距40mm两电压共振峰高且电压共振峰峰之间的电压输出比其他组合结构高.     

一种低成本压电无阀微泵的研制

提出了一种低成本的由压电材料驱动的平面扩张/收缩管无阀微泵的制作工艺.通过数值模拟确定了扩张/收缩管扩张角的最优值,在此基础上,采用光刻和湿法刻蚀工艺,刻蚀了300μm深的泵腔基片和100 μm深的盖片;使用等离子体清洗技术将其与PDMS薄膜键合,完成了可以实现单向泵送的压电无阀微泵样机制作.研究了该压电无阀微泵样机的...     

On using reservoir computing for sensing applications: exploring environment-sensitive memristor networks

Abstract

Recently, the SWEET sensing setup has been proposed as a way of exploiting reservoir computing for sensing. The setup features three components: an input signal (the drive), the environment and a reservoir, where the reservoir and the environment are treated as one dynamical system, a super-reservoir. Due to the reservoir-environment interaction, the information about the environment is encoded in the state of the reservoir. This information can be inferred (decoded) by analysing the reservoir state. The decoding is done by using an external drive signal. This signal is optimised to achieve a separation in the space of the reservoir states: Under different environmental conditions, the reservoir should visit distinct regions of the configuration space. We examined this approach theoretically by using an environment-sensitive memristor as a reservoir, where the memristance is the state variable. The goal has been to identify a suitable drive that can achieve the phase space separation, which was formulated as an optimization problem, and solved by a genetic optimization algorithm developed in this study. For simplicity reasons, only two environmental conditions were considered (describing a static and a varying environment). A suitable drive signal has been identified based on intuitive analysis of the memristor dynamics, and by solving the optimization problem. Under both drives the memristance is driven to two different regions of the one-dimensional state space under the influence of the two environmental conditions, which can be used to infer about the environment. The separation occurs if there is a synchronisation between the drive and the environmental signals. To quantify the magnitude of the separation, we introduced a quality of sensing index: The ability to sense depends critically on the synchronisation between the drive and environmental conditions. If this synchronisation is not maintained the quality of sensing deteriorates.     

A 10 GHz multiphase LC VCO with a ring capacitive coupling structure

A multiphase LC voltage-controlled oscillator(VCO) with a novel capacitive coupling CL ladder filter structure is proposed in this paper and this 10 GHz eight-phase VCO is applied in clock and data recovery(CDR) circuit for 40 Gb/s optical communications system.Compared with the traditional eight-phase oscillator,this capacitive coupling structure can decrease the number of inductors to half and only of four inductors.The VCO is designed and taped out in TSMC 65 nm CMOS technology.Measurement results show the phase noise is 105.95 dBc/Hz at 1MHz offset from a carrier frequency of 10 GHz.The chip area of VCO is 480 μm×700 μm and the VCO core power dissipation is 4.8 mW with the 1.0 V supply voltage.     

Low Voltage Electrowetting-on-Dielectric Platform using Multi-Layer Insulators

A low voltage, two-level-metal, and multi-layer insulator electrowetting-on-dielectric (EWD) platform is presented. Dispensing 300pl droplets from 140nl closed on-chip reservoirs was accomplished with as little as 11.4V solely through EWD forces, and the actuation threshold voltage was 7.2V with a 1Hz voltage switching rate between electrodes. EWD devices were fabricated with a multilayer insulator consisting of 135nm sputtered tantalum pentoxide (Ta(2)O(5)) and 180nm parylene C coated with 70nm of CYTOP. Furthermore, the minimum actuation threshold voltage followed a previously published scaling model for the threshold voltage, V(T), which is proportional to (t/ε(r))(1/2), where t and ε(r) are the insulator thickness and dielectric constant respectively. Device threshold voltages are compared for several insulator thicknesses (200nm, 500nm, and 1μm), different dielectric materials (parylene C and tantalum pentoxide), and homogeneous versus heterogeneous compositions. Additionally, we used a two-level-metal fabrication process, which enables the fabrication of smaller and denser electrodes with high interconnect routing flexibility. We also have achieved low dispensing and actuation voltages for scaled devices with 30pl droplets.     

An Ultra-Low Power Area Efficient Voltage Controlled Oscillator Based on Tunable Active Inductor for Wireless Applications.

This paper presents a tunable active inductor based ultra-low power, low area voltage-controlled oscillator (VCO) in 90 nm CMOS process. In the designed VCO, the modified topology of the active inductor is employed along with tuning capability. The layoutbased simulation has been performed deeming parasitic resistances and capacitances. The designed VCO yields an oscillation frequency ranging from 1.38 GHz to 3.16 GHz with a tuning range of 78.41%, where the tuning voltage is driven from 0.4 V to −0.2 V. The power dissipation varies from 0.062 mW to 0.177 mW, and the VCO provides a differential output power of 8.34 dBm to 3.94 dBm. The phase noise varies from −71 dBc/Hz to −65.4 dBc/Hz, and the Figure of Merit (FoM) has a value of −143.09 dBc/Hz @ 2.79 GHz frequency. The process corner analysis, temperature swept analysis, and Monte Carlo analysis of the proposed VCO had been carried out for the evaluation of its compatibility for diversified environments. Furthermore, the exclusion of the MOS varactor has condensed total silicon area consumption (10.3 μm × 8.5 μm). Finally, the designed VCO's performance parameters have been compared with mentioned designs where it is demonstrated that the designed VCO outdoes the others in most cases along with outstanding outcomes of low power and low silicon area consumption.     

一种两级误差放大器结构的LDO设计

基于SMIC 0.18μm CMOS工艺,设计了一种两级误差放大器结构的LDO稳压器。该电路运用两级误差放大器串联方式来改善LDO的瞬态响应性能,采用米勒频率补偿方式提高其稳定性。两级放大器中主放大器运用标准的折叠式共源共栅放大器,决定了电路的主要性能参数;第二级使用带有AB类输出的快速放大器,用来监控LDO输出电压的变化,以快速地响应此变化。电路仿真结果显示:在电源电压为5 V时,输出为1.8 V,输出电压的温度系数为10×10-6/℃;当电源电压从4.5 V到5.5 V变化时,线性瞬态跳变为48 mV;当负载电流从0 mA到60 mA变化时,负载瞬态跳变为5 mV。且环路的相位裕度为74°,整个电路的静态电流为37μA。该电路结构的瞬态跳变电压值远小于其他电路结构,且能实现低功耗供电。     

Design of a 4.2–5.4 GHz differential LC VCO using 0.35 μm SiGe BiCMOS technology for IEEE 802.11a applications

In this paper, a 4.2–5.4 GHz, ?Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high‐speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post‐layout simulation results, phase noise is ?110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and ?113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation‐mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm² on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.