Application of selective silicon epitaxial growth for CMOS technology

The application of selective silicon epitaxial growth for device isolation is described. An improved selective epitaxial isolation technology is presented in the fabrication of CMOS LSI. This advanced process technology results from a superior selectivity for selective silicon deposition. A CMOS ring oscillator with a twin-well structure is fabricated by using this selective epitaxial isolation technology. The feasibility of using an oversized contact, due to the nature of its steeper oxide-to-silicon isolation boundary, is demonstrated.     

Microstructural examination of extended crystal defects in silicon selective epitaxial growth

Selective epitaxial growth has been used to produce electronically isolated devices. The oxide/silicon interfaces in such materials are often associated with regions of poor device performance. In this study, the extended defects in the bulk near interfacial regions are examined by transmission electron microscopy. Process modifications suggest a large portion of the defects were due to thermal expansion mismatch and can be avoided.     

A novel 3-D BiCMOS technology using selective epitaxy growth (SEG)and lateral solid phase epitaxial (LSPE)

In this paper, a novel three-dimensional (3-D) BiCMOS technology is proposed and demonstrated. In this technology, the NMOS transistor is fabricated on the bulk substrate (bottom layer) and the PMOS transistor is fabricated on the single-crystal top layer obtained using the selective epitaxy growth (SEG) and lateral solid phase epitaxy (LSPE). In addition, the BJT is fabricated in the SEG region. The mobility of the PMOS transistors fabricated on the top layer is only approximately 5% lower than that of the PMOS fabricated on SOI, and the BJTs also have high performance with a peak f_T of 17 GHz and f_max of 14 GHz at V_ce=3 V. This 3-D BiCMOS technology is very promising for low power, high speed, and high frequency integrated circuit applications     

Selective silicon epitaxial growth for device-isolation technology

Selective silicon epitaxial growth using the SiH₂Cl₂/HCl/H₂ system under reduced pressure was accomplished in windows surrounded by a fine patterned insulator film on a silicon substrate. Selectivity, surface planarity, and facet formation were studied as a function of growth pressure, growth temperature, and HCl flow rate during selective epitaxial growth. Defects, which were mostly pairs of stacking faults, were observed along sidewalls. The defect density in the epi-layer decreased with both decreasing growth temperature and increasing HCl flow rate. Electrical properties of p-n junctions fabricated in the epi-layers were investigated. Polysilicon gate MOSFETs were successfully fabricated on the epitaxial silicon layers. It was revealed that the selective epitaxial growth isolation was effective to reduce latch-up susceptibility for CMOS circuits. It has been discovered that the selective epitaxial growth is applicable to fine and deep isolation and can realize submicron geometry isolation for VLSI.     

Confined lateral selective epitaxial growth of silicon for devicefabrication

An epitaxy technique, confined lateral selective epitaxial growth (CLSEG), which produces wide, thin slabs of single-crystal silicon over insulator, using only conventional processing, is discussed. As-grown films of CLSEG 0.9 μm thick, 8.0 μm wide, and 500 μm long were produced at 1000°C at reduced pressure. Junction diodes fabricated in CLSEG material show ideality factors of 1.05 with reverse leakage currents comparable to those of diodes built in SEG homoepitaxial material. Metal-gate p-channel MOSFETs in CLSEG with channel dopings of 2×10¹⁶ cm^-3 exhibit average mobilities of 283 cm²/V-s and subthreshold slopes of 223 mV/decade     

The pattern dependence of selectivity in low pressure selective epitaxial silicon growth

The dependence of selectivity on HC1 flow and operating pressure for an 850° C SiH₂Cl₂/ HC1 based SEG process has been investigated. The polysilicon nuclei density (#/cm² measured by optical microscope) on large unpatterned areas of deposited SiO₂ was used to quantify the selectivity of different process conditions. Three distinct selectivity regimes were identified: (a) a non-selective regime with >10⁶ nuclei/cm², (b) a pattern dependent regime with <10⁶ nuclei/cm², and (c) an intrinsically selective regime with <1 nuclei/cm². The intermediate, pattern dependent, selectivity regime was characterized by a much lower density of silicon nuclei in and around patterned areas where windows of Si are exposed, thus making a loss of selectivity more difficult to detect. This phenomenon is shown to arise from feature scale (<100 micron) lateral fluxes of gas phase species. An intrinsically selective regime suitable for VLSI manufacturing, which avoids the high nuclei density associated with the pattern dependent regime, is identified.     

Elimination of mesa-sidewall gate leakage in InAlAs/InGaAsheterostructures by selective sidewall recessing

Conventional mesa isolation in InAlAs/InGaAs HFETs results in the gate coming in contact with the exposed channel at the mesa sidewall, forming a parasitic gate-leakage path. The authors propose a simple method of recessing the channel edge into the mesa sidewall using a succinic-acid-based selective etchant for InGaAs over InAlAs. SEM photographs confirm the recessing of the channel along the sidewall. Special heterostructure diodes, designed with varying amounts of mesa-sidewall/gate-metal overlap, were fabricated with and without the sidewall isolation step. Electrical measurements confirm the complete elimination of sidewall leakage. for both diodes and HFETs     

A new technology for manufacturing the dielectric isolation of elements of microelectronic devices by oxidizing grooves in single-crystal silicon

The formation of the dielectric isolation of elements of microelectronic devices by oxidizing grooves in single-crystal silicon is considered. The new technological process makes it possible to shorten the manufacturing cycle and to improve the reliability and parameters of devices. It is shown that this result is attained by substantially shortening the time of oxidation of silicon, suppressing the “bird’s beak” irregularity, and reducing the capacitance of the metal-insulator-semiconductor structure through the etching of grooves with certain geometric parameters in silicon nitride. These parameters are the groove width 0.5–1.5 μm, the ratio of the width to the spacing between the grooves 0.56: 0.44, and the groove depth, which is larger than the width. The results of two-dimensional physical simulation support the advantages of the new technology over the standard process. The simulation was accomplished with the use of the SSUPREM4 program of the Silvaco bundled software.     

Parallel langmuir processes for silicon epitaxial growth in a SiHCl3-SiHx-H2 system

Parallel surface reactions in a SiHCl₃-SiH_x-H₂ system were numerically evaluated based on the heat and gas flow in the epitaxial reactor for clarifying the increase in the silicon epitaxial growth rate. H₂ and SiH_x are assumed to individually react with the intermediate surface species, *SiCl₂, which was formed by the chemisorption of SiHCl₃. The measurement was reproduced by the calculation using the rate constant obtained in this study for the surface reaction between *SiCl₂ and SiH_x. The decrease in the surface coverage by *SiCl₂ and the increase in the silicon yield were shown to be caused by the SiH_x. Thus, the surface reaction of the *SiCl₂ with the SiH_x was theoretically shown to be effective for increasing the growth rate to higher than the saturated value in an ordinary SiHCl₃-H₂ system. The rate equation for the parallel Langmuir processes in a general form was also described.     

Distinctive features of molecular-beam epitaxial growth of silicon on Si (100) surfaces in the presence of arsenic

The authors of this paper discuss their studies of the influence of background arsenic pressure on the properties of autoepitaxial layers of silicon grown on Si (100) surfaces by molecular-beam epitaxy. In these investigations the following experimental techniques were used: reflection high-energy electron diffraction (RHEED), scanning tunneling microscopy, x-ray photoelectron spectroscopy, and secondary ion mass spectrometry. Fiz. Tekh. Poluprovodn. 33, 1158–1163 (October 1999)     

沟槽式肖特基用高均匀性硅外延支撑层高速生长工艺研究

作为沟槽式肖特基芯片的关键支撑层,硅外延层的性质对芯片性能构成重要影响。系统探索了新式高速外延生长工艺制备硅外延层的方法。通过干涉显微镜、FT-IR、Hg-CV对硅外延层性质进行表征。研究了高速外延生长条件下的厚度均匀性、电阻率均匀性、表面完整性与外延反应流场、热场的作用规律。研究结果表明,通过基座高度的调制、加热功率的分配、预先基座包硅、本征覆盖层生长等综合手段解决了外延层边缘参数控制问题,并实现了最高6.6μm/min的生长速率。     

Simulation and implementation of a porous silicon reflector for epitaxial silicon solar cells

One of the main challenges in the ongoing development of thin film crystalline silicon solar cells on a supporting silicon substrate is the implementation of a long‐wavelength reflector at the interface between the epitaxial layer and the substrate. IMEC has developed such a reflector based on electrochemical anodization of silicon to create a multi‐layer porous silicon stack with alternating high and low porosity layers. This innovation results in a 1–2% absolute increase in efficiency for screenprinted epitaxial cells with a record of 13·8%. To reach a better understanding of the reflector and to aid in its continued optimization, several extensive optical simulations have been performed using an in‐house‐developed optical software programme. This software is written as a Microsoft Excel workbook to make use of its user‐friendliness and modular structure. It can handle up to 15 individual dielectric layers and is used to determine the influence of the number and the sequence of the layers on the internal reflection. A sensitivity analysis is also presented. A study of the angle at which the light strikes the reflector shows separate regions in the physical working of the reflector which include a region where the Bragg effect is dominant as well as a region where total internal reflection plays the largest role. The existence of these regions is proved using reflection measurements. Based on these findings, an estimate is made for the achievable current gain with an ideal reflector and the potential of epitaxial silicon solar cells is determined. Copyright © 2008 John Wiley & Sons, Ltd.     

引入GaN过渡层对Si（111）衬底上生长GaN外延的影响

本文研究了在Si(111)衬底上生长GaN外延层的方法。相比于直接在AlN缓冲层上生长GaN外延层,引入GaN过渡层显著地提高了外延层的晶体质量并降低了外延层的裂纹密度。使用X射线双晶衍射仪、光学显微镜以及在位监测曲线分析了GaN过渡层对外延层的晶体质量以及裂纹密度的影响。实验发现,直接在AlN缓冲层上生长外延层,晶体质量较差, X射线(0002)面半高宽最优值为0.686°,引入GaN过渡层后,通过调整生长条件,控制岛的长大与合并的过程,从而控制三维生长到二维生长过渡的过程,外延层的晶体质量明显提高, (0002)面半高宽降低为0.206°,并且裂纹明显减少。研究结果证明,通过生长合适厚度的GaN过渡层,可以得到高质量、无裂纹的GaN外延层。     

Improved hot-electron degradation in nMOSFETs with elevated source and drain structures realised by selective epitaxial growth of silicon using silane only

For the first time, n-channel MOSFETs with elevated source and drain structures, realised by selective epitaxial growth (SEG) of silicon using silane only, have been stressed under various conditions. Depending on the gate voltage, up to ten times improvement in hot-electron related degradation has been observed compared with the standard MOSFET structure. This has been attributed to the alleviation and spreading of the lateral electric field near the drain end of the transistor because of the very shallow and graded junctions obtained in elevated S/D structures.<>     

Evaluation of binary and ternary melts for the low temperature liquid phase epitaxial growth of silicon

Liquid-phase-epitaxy allows the growth of good quality layers at low temperature, although this advantage is yet to be fully exploited for silicon. Silicon solubility was investigated in a range of binary and ternary metal alloys to identify suitable low temperature combinations. Gold based alloys were determined to be the most suitable for the growth of lightly doped layers, with Au-Bi and Au-Pb alloys giving high silicon solubilities at temperatures below 400° C. Liquid-phase-epitaxy of silicon was demonstrated over the 380–450° C range from such alloys.     

Fabrication of InP-based InGaAs ridge quantum wires utilizing selective molecular beam epitaxial growth on (311)A facets

InP-based InGaAs/InAlAs ridge quantum wires were successfully fabricated by our new approach using selective molecular beam epitaxy (MBE). As the starting structures, array of InGaAs ridge structures composed of smooth (311)A facets were formed by MBE on mesa-patterned InP substrates. Prior to actual fabrication of the wires, MBE growth characteristics of In_0.53Ga_0.47As and In_0.52Al_0.48As layers on the starting structure were studied in detail. The results of growth experiments were then successfully applied to the fabrication of InGaAs ridge quantum wires with high spatial uniformity. Low temperature cathodoluminescence spectrum measured in response to spot excitation of wire region showed a strong light emission whose analysis indicated that it originates from InGaAs ridge quantum wire itself. In photoluminescence measurements, the emission from the wire had strong intensity even at room temperature, indicating that the wire crystal possesses excellent bulk and interface quality, and are largely free from nonradiative recombination centers.     

Nearly bird's beak-free local oxidation technology for controlled dielectric formation in deep silicon trenches

Silicon deep trench isolation technology using local oxidation is reported. Scaled, high-density trench capacitors were fabricated with varying trench aspect ratios. Nearly bird's beak-free local oxidation resulted in a controlled growth of silicon dioxide on the trench bottom surfaces and significantly improved the trench gate MOS isolation characteristics. Detailed MOS capacitance measurements were performed and wafer yield in excess of 90% was demonstrated across 4 inch diameter silicon wafers.<>     

Molecular-beam epitaxial growth of HgCdTe infrared focal-plane arrays on silicon substrates for midwave infrared applications

Molecular beam epitaxy has been employed to deposit HgCdTe infrared detector structures on Si(112) substrates with performance at 125K that is equivalent to detectors grown on conventional CdZnTe substrates. The detector structures are grown on Si via CdTe(112)B buffer layers, whose structural properties include x-ray rocking curve full width at half maximum of 63 arc-sec and near-surface etch pit density of 3–5 × 10⁵ cm⁻² for 9 μm thick CdTe films. HgCdTe p⁺-on-n device structures were grown by molecular beam epitaxy (MBE) on both bulk CdZnTe and Si with 125K cutoff wavelengths ranging from 3.5 to 5 μm. External quantum efficiencies of 70%, limited only by reflection loss at the uncoated Si-vacuum interface, were achieved for detectors on Si. The current-voltage (I-V) characteristics of MBE-grown detectors on CdZnTe and Si were found to be equivalent, with reverse breakdown voltages well in excess of 700 mV. The temperature dependences of the I-V characteristics of MBE-grown diodes on CdZnTe and Si were found to be essentially identical and in agreement with a diffusion-limited current model for temperatures down to 110K. The performance of MBE-grown diodes on Si is also equivalent to that of typical liquid phase epitaxy-grown devices on CdZnTe with R₀A products in the 10⁶–10⁷ Θ-cm² range for 3.6 μm cutoff at 125K and R₀A products in the 10⁴–10⁵ Θ-cm² range for 4.7 μm cutoff at 125K.     

Selective silicon epitaxial growth on a submicrometer WSi2 grating: Application to the permeable base transistor

We report the silicon epitaxial growth on top of a tungsten disilicide grating using a rapid thermal processing, low pressure chemical vapor deposition reactor. The epitaxial growth of silicon is shown to proceed two dimensionally from the Si surface without reaction with the underlying WSi₂ grid. Both lateral diffusion over WSi₂ of Si adsorbed species and vertical diffusion of Si through the silicide film are shown to occur with respective weight depending on the width of the WSi₂ lines. This allows silicon selective growth on patterned Si/WSi₂ structure for grating periodicity below 1 μm. Preliminary electrical measurements of the Si/WSi₂/Si overgrown permeable base transistor (PBT) thus fabricated are presented, showing current densities J_max of up to 6000 A/cm² and transconductancesg _m of 5 mS/mm.