基于片上网络的容错通信方法

本文提出了一种基于片上网络的容错通信算法。若NoC中出现路由器或者链路故障,将导致NoC不能有效地进行通信。本方案为每个路由器的输出端口配置输出状态寄存器,标识出输出端口所连接的路由器或链路的故障状态,从而建立起一个新的容错模型,在路由时采用新的可重构路由算法避免这些故障的路由器和链路,从而达到保证NoC有效通信的目的。本文在5×52D-Mesh结构上仿真了所提出的方案,统计了数据传输时延,实验结果表明,与现有方案相比,这种方法能够在保证容忍NoC中路由器和链路故障的前提下,获得较低的通信时延。     

WiNoC中无线通信拥塞与故障感知的容错路由算法

在无线片上网络中,无线通信拥塞和故障对整个片上网络的通信效率具有严重影响.为此本文提出了一种针对无线通信拥塞和故障的容错路由算法,首先设计了无线通信拥塞和故障感知模型,该模型能够感知无线节点通信对的拥塞和故障信息,并对其编码发送给子网中的路由器;然后子网中的路由器根据接收到的无线节点通信对状态信息,判断数据包是否使用无线传输.实验表明,本文方案相较于对比对象能够在较小的额外面积、功耗开销下,保证较低的网络延迟和较高的网络吞吐率,并对无线节点通信对的永久性故障具有良好的容错能力.     

针对路径故障与局部拥塞的NoC容错路由算法

片上网络作为一种新型片上互连架构,克服了片上系统在发展中遭遇的瓶颈问题。然而,片上网络中的路由器故障以及路由器之间的链路故障都会造成网络性能损失。对此,文章提出一种针对路径故障与局部拥塞的NoC容错路由算法。首先,设计了一种相隔节点间路径故障模型,该模型下的路由器以较小的开销为代价,动态感知两跳以内的路径故障状态。其次,提出了一种新颖的更能准确反映局部网络拥塞状态的拥塞模型来均衡网络流量。最后,当网络无故障时,算法保证走最优路径;有故障时,算法不仅可以实现容错还能保证网络具有良好的性能。实验表明,在无故障的情况下,本文方案相较于对比对象延迟降低了10％～20％,吞吐率提高了25％左右。在有故障的情况下,本文方案较对比对象的优势更加明显。     

接口标记容错路由算法

随着片上系统(SoC)集成度的不断提高,IP核之间的通信故障成为亟待解决的问题,片上网络(NoC)是解决SoC通信问题的有效途径。容错路由算法是NoC设计中的关键技术,对NoC的通信效率有重要影响。在Valiant随机路由算法和源路由算法的基础上,提出了一种接口标记容错路由算法。该算法吸取了Valiant随机路由算法能平衡网络负载、降低拥塞概率的优良性能与源路由算法中路径不需要计算与查找的特点,减小了传输时延,提高了路由器的利用率。     

一种面向应用的NoC容错路由算法

随着芯片集成度的不断提高,芯片制造工艺进入深亚微米级以后,片上将会出现更多难以预测与消除的故障类型。为了实现可靠的片上通信,应用容错机制与算法是一个重要的解决方案。本文提出一种面向应用的NoC容错路由算法,该算法在重负载时使用带有部分故障的链路并使流量在网络中均匀分布。同时给出了实现该算法需要的扩展后的路由器结构。仿真结果表明,所提出的路由算法与现有的路由算法相比,具有更好的时延性能。     

多层卫星网络链路中断容忍路由策略设计

链路中断和接续对卫星网络路由有重要影响,该文针对多层卫星网络,设计了链路中断容忍路由策略,利用非均匀时间段内卫星网络拓扑结构的可预测性进行路由表计算,采取动态的拥塞控制机制和洪泛策略,解决由于卫星运动、通信设备故障引发链路中断情况下的路由问题。仿真结果表明,该路由策略具有较高的链路利用率,能够减少动态路由计算中时延信息收集和星上路由表生成给卫星节点带来的时空开销。     

一种自适应的混合型无线NoC拓扑结构

针对传统大规模片上网络（Network-on-Chip,NoC）远距离核间多跳通信所带来的高能耗与延时问题,提出了一种基于虚Torus的自适应的混合型无线NoC拓扑结构（VT-AWiNoC）．该结构通过引入链路拥塞测度作为感知参数,基于此采用热点无线链路自动探测与带宽动态分配机制,并设计实现发送器动态分配的控制电路模块,以达到根据不同的通信流量模型,于片内自适应地调整拓扑结构及链路带宽的目的．通过建立混合型无线NoC的延时与功耗评估模型,对该结构的无线NoC进行性能评估．实验结果表明,该自适应拓扑与其它混合型无线NoC相比,在随机流量模型下,网络平均延时降低了16．52～23．27％;在20％的热点流量模型下,包平均能耗节省了39．19％;以真实应用FFT作为基准测试,平均延时降低了17．20％～21．68％,并节省了23．49％的包平均能耗．该结构以较小的面积开销获得了更优的性能．     

基于包交换技术的可重构片上网络混合路由器设计

在非密集计算任务下,分布式路由片上网络表现出良好的性能.然而当片上网络布局密度接近1时,受算法制约,高链路拥塞率会严重降低分布式路由网络执行大批量数据传输任务的性能.考虑到片上网络需传输数据的密集/非密集特征,由此设计集成有可定向传输事务的混合式路由,通过配置路由节点分配两种路由策略的权限,在片上网络中构建点对点高权限专用数据链路,避免分布式路由自寻链路带来网络长时拥塞、事务处理迟延问题,保证事务并行度,提高网络节点挂载计算核布局的容忍度.同时论文在8×8Mesh结构下对集成有混合路由网络性能进行了测试,结果表明采用混合路由有效提高了传输带宽和链路成功率等网络性能指标.     

基于HERMES NoC的片上网络容错方法研究

为解决片上网络的可靠性问题,以HERMES NoC(Network-on-Chip)为基础,首先设计了具有容错功能的HERMES交换器;同时提出了基于HERMES的端到端、交换到交换的前向纠错(FEC)和检错重发(ARQ)的容错机制。最后对采用Ham-ming、DAP、BSC三种码的容错机制进行了仿真综合,比较了六种容错机制的面积、延迟和功耗开销。结果显示面积节省型比低延迟交换到交换和端到端更节省开销,DAP码面积和功耗开销最小,但重传却具有更好的容错性能。     

基于包-电路交换的片上网络回退转向路由算法

采用包-电路交换的片上路由器,链路的建立通过发送请求包完成,而数据的传输则采用电路形式。传统的路由算法已经不能很好地适应基于包-电路交换的片上网络(NoC)新特性。该文根据包-电路交换的NoC的特点,提出了一种新的路由算法回退转向(RT)路由算法,以改善NoC性能。实验结果表明,与动态XY路由算法相比,回退转向路由算法使得网络平均吞吐量和平均包延迟最大分别改善26.7%和11.6%。     

Performance evaluation of a routing algorithm based on Hopfield Neural Network for network-on-chip

Network on chip (NoC) has emerged as a solution to overcome the system on chip growing complexity and design challenges. A proper routing algorithm is a key issue of an NoC design. An appropriate routing method balances load across the network channels and keeps path length as short as possible. This survey investigates the performance of a routing algorithm based on Hopfield Neural Network. It is a dynamic programming to provide optimal path and network monitoring in real time. The aim of this article is to analyse the possibility of using a neural network as a router. The algorithm takes into account the path with the lowest delay (cost) form source to destination. In other words, the path a message takes from source to destination depends on network traffic situation at the time and it is the fastest one. The simulation results show that the proposed approach improves average delay, throughput and network congestion efficiently. At the same time, the increase in power consumption is almost negligible.     

Performance analysis of minimal path fault tolerant routing in NoC

Occurrence of faults in Network on Chip (NoC) is inevitable as the feature size is continuously decreasing and processing elements are increasing in numbers. Faults can be revocable if it is transient. Transient fault may occur inside router, or in the core or in communication wires. Examples of transient faults are overflow of buffers in router, clock skew, cross talk, etc.. Revocation of transient faults can be done by retransmission of faulty packets using oblivious or adaptive routing algorithms. Irrevocable faults causes non-functionality of segment and mainly occurs during fabrication process. NoC reliability increases with the efficient routing algorithms, which can handle the maximum faults without deadlock in network. As transient faults are temporary and can be easily revoked using retransmission of packet, permanent faults require efficient routing to route the packet by bypassing the nonfunctional segments. Thus, our focus is on the analysis of adaptive minimal path fault tolerant routing to handle the permanent faults. Comparative analysis between partial adaptive fault tolerance routing West-First, North-Last, Negative-First, Odd Even, and Minimal path Fault Tolerant routing (MinFT) algorithms with the nodes and links failure is performed using NoC Interconnect RoutinG and Application Modeling simulator (NIRGAM) for the 2D Mesh topology. Result suggests that MinFT ensures data transmission under worst conditions as compared to other adaptive routing algorithms.     

片上网络节点编码的设计和在路由方面的应用

网络拓扑选择和路由算法设计是片上网络设计的关键问题.在比较现有的三种网络拓扑结构的基础上,提出了一种隐含着相邻节点以及节点之间链路关系并适合二维Torus拓扑结构的节点编码方法.该编码和Torus结构的结合能拓扑结果够简化路由算法的设计和实现,改善了网络路由性能.实验结果表明,提出的编码方法与二维Torus拓扑结构的结合有效地提高了片上网络通信性能.     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

SRNoC: A novel high performance Shared-Resource routing scheme for Network-on-Chip

This paper proposes a novel Shared-Resource routing scheme, SRNoC, that not only enhances network transmission performance, but also provides a high efficient load-balance solution for NoC design. The proposed SRNoC scheme expands the NoC design space and provides a novel effective NoC framework. SRNoC scheme mainly consists of the topology and routing algorithm. The proposed topology of SRNoC is based on the Shared-Resource mechanism, in which the routers are divided into groups and each group of routers share a set of specified link resource. Because of the usage of Shared Resource mechanism, SRNoC could effectively distribute the workload uniformly onto the network so as to improve the utilization of the resource and alleviate the network congestion. The proposed routing algorithm is a minimal oblivious routing algorithm. It could improve average latency and saturation load owing to its flexibility and high efficiency. In order to evaluate the load-balance property of the network, we proposed a method to calculate the Φ which represents the characteristic value of load-balance. The smaller the Φ, the better the performance in load-balance. Simulation results show that the average latency and saturation load are dramatically improved by SRNoC both in synthetic traffic patterns and real application traffic trace with negligible hardware overhead. Under the same simulation condition, SRNoC could cut down the total network workload to 48.67% at least. Moreover, SRNoC reduces the value of Φ 45% at least compared with other routing algorithms, which means it achieves better load-balance feature.     

基于动态路径诱导的网络路由技术

随着网络规模的不断扩大,一些基于纯数学模型的路由算法已经面临新的挑战。针对网络路由对实时性和可靠性的要求,采用动态路径诱导算法对网络流量进行实时预测,可以解决传统的诱导算法存在的时变性差和收敛慢的问题。动态路径诱导算法基于神经网络时间预测模型和遗传算法,经仿真表明该动态路径诱导方法在网络繁忙时能显著改善网络路由性能。     

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip

We present a novel Partial Virtual channel Sharing (PVS) NoC architecture which reduces the impact of faults on performance and also tolerates faults within the routing logic. Without PVS, failure of a component impairs the fault-free connected components, which leads to considerable performance degradation. Improving resource utilization is key in enhancing or sustaining performance with minimal overhead when faults or overload occurs. In the proposed architecture, autonomic virtual-channel buffer sharing is implemented with a novel algorithm that determines the sharing of buffers among a set of ports. The runtime allocation of the buffers depends on incoming load and fault occurrence. In addition, we propose an efficient technique for maintaining the accessibility of a processing element (PE) to the network even if its router is faulty. Our techniques can be used in any NoC topology and for both, 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate 22 % reduction in average packet latency compared to state-of-the-art virtual channel (VC) based NoC architecture. Extensive quantitative simulation has been carried out with synthetic benchmarks. Simulation results reveal that the PVS architecture improves the performance significantly in presence of faults, compared to other VC-based NoC architectures.     

A Fault Tolerant Hierarchical Network on Chip Router Architecture

Continuing advances in the processing technology, along with the significant decreases in the feature size of integrated circuits lead to increases in susceptibility to transient errors and permanent faults. Network on Chips (NoCs) have come to address the demands for high bandwidth communication among processing elements. The structural redundancy inherited in NoC-based design can be exploited to improve reliability and compensate for the effects of failures. In this paper, we propose an enhanced fault tolerant microarchitecture with deadlock-free routing for Hierarchical NoCs. The proposed router supplies dynamic Virtual Channel (VC) Allocation, and it employs a high-performance fault tolerant control flow, handling both transient and permanent faults in hierarchical networks without extra retransmission buffer requirements. Experimental results show a significant improvement in reliability as well as decreases in the average latency and energy consumption.     

An interconnection architecture for network-on-chip systems

Network on Chip (NoC) is a discipline research path that primarily addresses the global communication in System on Chip (SoC). It is inspired and uses the same routing and switching techniques needed in multi-computer networks. Current shared-bus based on-chip communication architectures generally have limited scalability due to the nature of the buses especially when complex on-chip communication SoC is needed. The main goal is to have a dedicated communication infrastructure in the system that can scale up while minimizing the area and power. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we introduce a new NoC architecture by adapting a recursive topology structure. An experimental study is performed to compare this structure with basic NoC topologies represented by 2D mesh and Spidergon. The analysis illustrates the main features of this topology and its unique benefits. The simulation results show that recursive network outperforms 2D mesh and Spidergon in main performance metrics.