工艺变化下互连线分布参数随机建模与延迟分析

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,电路制造过程中的工艺变化已经成为影响集成电路互连线传输性能的重要因素.文中引入高斯白噪声建立了互连线分布参数的随机模型,并提出基于Elmore延迟度量的工艺变化下的互连延迟估计式;通过简化工艺变化量与互连线参数之间的关系式,对延迟一阶变化量与二阶变化量进行了分析,给出一般工艺变化下互连延迟的统计特性计算方法;另,针对线宽工艺变化推导出互连延迟均值与方差的计算公式.最后通过仿真实验对工艺变化下互连线延迟分析方法及其统计特性计算公式的有效性进行了验证.     

工艺变化下互连线建模与ABCD参数仿真

考虑互连线工艺变化的空间相关性,采用数值仿真及拟合方法,得到电气分布参数的近似表达式,建立了互连线分布参数随机模型;推导出互连线ABCD参数满足的随机微分方程组,并提出基于蒙特卡洛法的ABCD参数统计分析方法;最后,通过对ABCD参数各参量系数的正态性进行偏度-峰度检验,给出最差情况估计.实验结果表明,提出的互连线随机模型及统计分析方法可以对工艺变化下的互连线传输性能进行有效的评估.     

随机工艺变化下互连线ABCD参数建模与仿真

集成电路的不断发展使得互连线的随机工艺变化问题已经成为影响集成电路设计与制造的重要因素。基于电报方程建立了工艺变化下互连线的分布参数随机模型,推导出互连线ABCD参数满足的随机微分方程组,并提出了基于蒙特卡洛法的互连线ABCD参数统计分析方法,通过对ABCD参数各参量系数的正态性进行偏度-峰度检验,给出了最差情况估计。实验结果表明所提出的互连线随机模型及统计分析方法可以对工艺变化下的互连线传输性能进行有效的评估。     

VLSI中互连线工艺变化的若干问题研究进展

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,互连线的工艺变化已成为影响集成电路性能的重要因素.针对该问题,结合作者的研究工作,综述了目前国内外互连线工艺变化若干关键问题的研究进展情况,重点介绍工艺变化条件下互连线寄生电参数及其传输性能的研究方法,并分析不同技术的特点和局限性.最后展望了互连线工艺变化问题今后的研究发展方向.     

ULSI中的铜互连线RC延迟

随着ULSI向深亚微米特征尺寸发展，互连引线成为ULSI向更高性能发展的主要限制因素。由互连引线引起的串扰噪音及RC延迟限制了ULSI的频率性能的提高，同时考虑到电迁移和功率损耗，人们开始寻找新的互连材料；低电阻率的铜互连材料和低介电常数介质的结合可以有效地发送互连线的性能，主要讨论了互连延迟的重要性以及发送和计算延迟的方法。     

VLSI互连线系统中的低介电常数材料与工艺研究

阐述了超大规模集成电路 ( VLSI)特征尺寸的减小及互连线层数增加引起的互连线电容增加的问题。具体总结了为提高 VLSI的速度而采用的低介电常数材料及其制备工艺 ,对在连线间形成空气间隙来降低线间电容的方法也进行了介绍。最后 ,展望了低介电常数材料在 VL SI互连线系统中的应用前景。     

高速电路平行互连线时延估算与数值分析

利用数值方法分析了0．25μm工艺条件之下双平行线以及三平行线最坏情况下的时间延迟，得到了考虑驱劝电阻以及终端负载影响的时间延迟简单经验计算公式。该公式比文献上已有公式的适应范围更广，与Hspice精确仿真结果的误差在10％以内。     

基于工艺参数扰动的随机互连线时延分析

考虑工艺参数扰动对互连电路传输性能的影响,建立了基于工艺扰动的互连线随机模型.通过改进的去耦算法对随机互连线元进行去耦,结合随机伽辽金方法(SGM)和多项式混沌展开(PCE)进行互连分析,进而利用复逼近及二分法给出工艺参数扰动下互连时延的有限维表达式.仿真实验结果不仅与SPICE仿真吻合得较好,相较于SPICE蒙特卡洛仿真还具有更高的计算效率.     

ULSI/VLSI中铝互连线热应力的数值模拟

对有钝化层与无钝化层的铝互连线的热应力进行了数值模拟,并建立起互连线的二维有限元模型.对无钝化的铝互连线,只考虑弹性行为,其应力随线宽及衬底刚度的增加而增加.对于钝化的铝互连线,对其弹性行为和弹性/理想塑性行为进行了模拟.结果发现,互连线线宽的减小,钝化层硬度的增加,都会使应力增加.与纯弹性线条相比,弹性/理想塑性互连线条中的应力有所减小,且分布更均匀.     

Fast statistical delay evaluation of RC interconnect in the presence of process variations

Fast statistical methods of interconnect delay and slew in the presence of process fluctuations are proposed. Using an optimized quadratic model to describe the effects of process variations, the proposed method enables closed-form expressions of interconnect delay and slew for the given variations in relevant process parameters. Simulation results show that the method, which has a statistical characteristic similar to traditional methodology, is more efficient compared to HSPICE-based Monte Carlo simulations and traditional methodology.     

考虑工艺波动的快速RC互连延时统计计算

本文提出了一种考虑工艺波动影响的计算延时和过渡时间的快速统计模型。模型中使用优化的二阶模型描述工艺波动的影响,使用了闭合表达式来表示相关工艺参数和工艺波动影响下的延时和过渡时间之间的关系。仿真实验表明：提出的模型和传统算法有相似的精度和相似的统计特性,而计算效率大大高于基于HSPICE的模特卡罗分析和传统方法。     

Crosstalk-affected delay analysis in nanometer technologies

This article presents a detailed analysis of the crosstalk-affected delay of coupled interconnects considering process variations. We utilise a distributed RC-π model of the interconnections to accurately model process variations. In particular, we perform a detailed investigation of various crosstalk scenarios and study the impact of different parameters on crosstalk delay. Although accounting for the effect of correlations among parameters of the neighbouring wire segments, statistical properties of the crosstalk-affected propagation delays are characterised and discussed. Monte Carlo-based simulations using Spice demonstrate the effectiveness of the proposed approach in accurately modeling the correlation-aware process variations and their impact on interconnect delay in the presence of crosstalk.     

考虑工艺波动的RLC互连延时统计模型

基于概率解释算法的原理,提出了一种考虑工艺波动的RLC互连延时统计模型,该模型使用了对数正态分布函数。在给定互连参数波动范围条件下,利用该算法计算延时仅需要采用前两个瞬态。和HSPICE相比,Monte Carlo分析中的均值和平均偏差误差分别低于0.7％和0.51％。模型计算简单且精度高,可以满足互连线仿真要求。     

基于工艺参数扰动的随机互连线时延分析

考虑工艺参数扰动对互连电路传输性能的影响,建立了基于工艺扰动的互连线随机模型.通过改进的去耦算法对随机互连线元进行去耦,结合随机伽辽金方法(SGM)和多项式混沌展开(PCE)进行互连分析,进而利用复逼近及二分法给出工艺参数扰动下互连时延的有限维表达式.仿真实验结果不仅与SPICE仿真吻合得较好,相较于SPICE蒙特卡洛仿真还具有更高的计算效率.     

A cross-layer SER analysis in the presence of PVTA variations

As the technology scaling enters into the nanoscale regime, soft errors become one of the major challenging issues for VLSI chips. Susceptibility to soft error is even becoming more severe in the presence of workload-dependent Process, Voltage, Temperature, and Transistor Aging (PVTA) variations. In this paper, we propose a systematic cross-layer methodology to model and analyze the impact of different abstraction layers on the PVTA variations and in turn on the susceptibility of processors to soft error. To do so, the workload is divided into several fine-grained timing windows. Based on a top-down profiling approach, the effects of each window is projected into the circuit-level model of the processor in order to extract PVTA profiles of “each cell” in the circuit. Finally, at circuit-level, an “instance-based” simulation flow is exploited to capture both spatial and temporal PVTA-aware Soft Error Rate (SER) variations within/across applications for every functional block of the processor. The simulation results for various ITC’99 benchmark circuits and the LEON3 processor running different benchmark applications show that disregarding PVTA information results in significant error in the estimated SER.     

Low VDD and body bias conditions for testing bridge defects in the presence of process variations

Bridge defects are an important manufacturing defect that may escape test causing reliability issues. It has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods lowering test quality. Therefore, advances in test methodologies to enhance bridge detection are required. In this work a Statistical Timing Analysis Framework (STAF) is used to compute the probability of detection of bridge defects for different V_DD and RBB values. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage (SFC). The STAF allows to capture properly the behavior of the mean and a standard circuit delay when V_DD and RBB change. Furthermore, the STAF uses a realistic bridge defect model suitable to consider appropriately the impact of V_DD and RBB on delay increase. This methodology is applied to some ISCAS benchmark circuits implemented in a commercial 65 nm CMOS technology. The obtained results of several ISCAS benchmark circuits show clearly that the Statistical Fault Coverage (SFC) increases significantly when V_DD is lowered, and increases even more when RBB is applied at Low V_DD. The test conditions to improve resistive bridge detection combining Low V_DD and Reverse Body Bias (RBB) under a delay based test are determined. It is shown that the impact of RBB on bridge detection improves significantly for a sufficient low value of V_DD. The values of Low V_DD and RBB can be selected considering the tradeoff between fault coverage and test time penalization.