工艺变化下互连线分布参数随机建模与延迟分析

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,电路制造过程中的工艺变化已经成为影响集成电路互连线传输性能的重要因素.文中引入高斯白噪声建立了互连线分布参数的随机模型,并提出基于Elmore延迟度量的工艺变化下的互连延迟估计式;通过简化工艺变化量与互连线参数之间的关系式,对延迟一阶变化量与二阶变化量进行了分析,给出一般工艺变化下互连延迟的统计特性计算方法;另,针对线宽工艺变化推导出互连延迟均值与方差的计算公式.最后通过仿真实验对工艺变化下互连线延迟分析方法及其统计特性计算公式的有效性进行了验证.     

工艺变化下互连线建模与ABCD参数仿真

考虑互连线工艺变化的空间相关性,采用数值仿真及拟合方法,得到电气分布参数的近似表达式,建立了互连线分布参数随机模型;推导出互连线ABCD参数满足的随机微分方程组,并提出基于蒙特卡洛法的ABCD参数统计分析方法;最后,通过对ABCD参数各参量系数的正态性进行偏度-峰度检验,给出最差情况估计.实验结果表明,提出的互连线随机模型及统计分析方法可以对工艺变化下的互连线传输性能进行有效的评估.     

随机工艺变化下互连线ABCD参数建模与仿真

集成电路的不断发展使得互连线的随机工艺变化问题已经成为影响集成电路设计与制造的重要因素。基于电报方程建立了工艺变化下互连线的分布参数随机模型,推导出互连线ABCD参数满足的随机微分方程组,并提出了基于蒙特卡洛法的互连线ABCD参数统计分析方法,通过对ABCD参数各参量系数的正态性进行偏度-峰度检验,给出了最差情况估计。实验结果表明所提出的互连线随机模型及统计分析方法可以对工艺变化下的互连线传输性能进行有效的评估。     

VLSI中互连线工艺变化的若干问题研究进展

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,互连线的工艺变化已成为影响集成电路性能的重要因素.针对该问题,结合作者的研究工作,综述了目前国内外互连线工艺变化若干关键问题的研究进展情况,重点介绍工艺变化条件下互连线寄生电参数及其传输性能的研究方法,并分析不同技术的特点和局限性.最后展望了互连线工艺变化问题今后的研究发展方向.     

ULSI中的铜互连线RC延迟

随着ULSI向深亚微米特征尺寸发展，互连引线成为ULSI向更高性能发展的主要限制因素。由互连引线引起的串扰噪音及RC延迟限制了ULSI的频率性能的提高，同时考虑到电迁移和功率损耗，人们开始寻找新的互连材料；低电阻率的铜互连材料和低介电常数介质的结合可以有效地发送互连线的性能，主要讨论了互连延迟的重要性以及发送和计算延迟的方法。     

VLSI互连线系统中的低介电常数材料与工艺研究

阐述了超大规模集成电路 ( VLSI)特征尺寸的减小及互连线层数增加引起的互连线电容增加的问题。具体总结了为提高 VLSI的速度而采用的低介电常数材料及其制备工艺 ,对在连线间形成空气间隙来降低线间电容的方法也进行了介绍。最后 ,展望了低介电常数材料在 VL SI互连线系统中的应用前景。     

高速电路平行互连线时延估算与数值分析

利用数值方法分析了0．25μm工艺条件之下双平行线以及三平行线最坏情况下的时间延迟，得到了考虑驱劝电阻以及终端负载影响的时间延迟简单经验计算公式。该公式比文献上已有公式的适应范围更广，与Hspice精确仿真结果的误差在10％以内。     

基于工艺参数扰动的随机互连线时延分析

考虑工艺参数扰动对互连电路传输性能的影响,建立了基于工艺扰动的互连线随机模型.通过改进的去耦算法对随机互连线元进行去耦,结合随机伽辽金方法(SGM)和多项式混沌展开(PCE)进行互连分析,进而利用复逼近及二分法给出工艺参数扰动下互连时延的有限维表达式.仿真实验结果不仅与SPICE仿真吻合得较好,相较于SPICE蒙特卡洛仿真还具有更高的计算效率.     

ULSI/VLSI中铝互连线热应力的数值模拟

对有钝化层与无钝化层的铝互连线的热应力进行了数值模拟,并建立起互连线的二维有限元模型.对无钝化的铝互连线,只考虑弹性行为,其应力随线宽及衬底刚度的增加而增加.对于钝化的铝互连线,对其弹性行为和弹性/理想塑性行为进行了模拟.结果发现,互连线线宽的减小,钝化层硬度的增加,都会使应力增加.与纯弹性线条相比,弹性/理想塑性互连线条中的应力有所减小,且分布更均匀.     

A cross-layer SER analysis in the presence of PVTA variations

As the technology scaling enters into the nanoscale regime, soft errors become one of the major challenging issues for VLSI chips. Susceptibility to soft error is even becoming more severe in the presence of workload-dependent Process, Voltage, Temperature, and Transistor Aging (PVTA) variations. In this paper, we propose a systematic cross-layer methodology to model and analyze the impact of different abstraction layers on the PVTA variations and in turn on the susceptibility of processors to soft error. To do so, the workload is divided into several fine-grained timing windows. Based on a top-down profiling approach, the effects of each window is projected into the circuit-level model of the processor in order to extract PVTA profiles of “each cell” in the circuit. Finally, at circuit-level, an “instance-based” simulation flow is exploited to capture both spatial and temporal PVTA-aware Soft Error Rate (SER) variations within/across applications for every functional block of the processor. The simulation results for various ITC’99 benchmark circuits and the LEON3 processor running different benchmark applications show that disregarding PVTA information results in significant error in the estimated SER.     

基于Monte Carlo方法的任意概率密度随机数字信号发生器设计

在信号处理和计算机微观模拟的过程中,经常要构造具有特定概率密度的随机数发生器.采用常规方法实现难度较大且不具普遍性,本文根据Monte Carlo方法基本原理和随机信号的数字特征给出一种任意概率密度随机数发生器的设计方法及核心源代码.实验证明该方法简单高效、通用性好.     

Impact of Al in Cu alloy interconnects on electro and stress migration reliabilities

The reliability of Cu interconnects was successfully improved by applying a CuAl alloy seed. However, the effect of additive Al on the reliability is not fully understood. In order to reveal the reliability improvement mechanism, Cu films using CuAl alloy seed were investigated in detail. As stress induced voiding (SIV) as well as electromigration is caused by migration of vacancies and/or Cu atoms, the measured activation energy value of electromigration using CuAl indicates that the fast diffusion paths are Cu grain boundaries. The analysis using high lateral resolution scanning type secondary ion mass spectrometry (nano-SIMS) clarifies that additive Al in ECP-Cu film is mainly localized at grain boundaries. Furthermore, positron annihilation was used to probe vacancy-type defects in Cu films. The CuAl films before recrystallization contain larger and higher density vacancy-type defects. Whereas, the recrystallized CuAl films after annealing above 250 °C contain smaller and lower density defects. Furthermore, CuAl films with annealing above 350 °C contain less Al inside the grains. These results represent that Al atoms in Cu films with annealing above 350 °C are exhausted from inside grains to the grain boundaries, and the spewed Al atoms existing at Cu grain boundary effectively prevents the diffusion of Cu and/or vacancies.     

Small-delay defect detection in the presence of process variations

Interconnect-based defects such as partial opens are becoming more prevalent in nanoscale designs. These are latent defects that affect circuit reliability and can be modeled as small-delay defects. Detecting such defects therefore requires faster than at-speed test clocks. In the paper we analyze the uncertainty introduced by process variations in detecting these defects. We propose new path selection algorithms that increase the probability of defect detection by taking into account the variability in path delays. Our results show that the new technique detects much smaller defects than the traditional approach of selecting the longest paths for test.     

Effect of stresses on the evolution of annealing textures in Cu and Al interconnects

A new model is advanced to account for the evolution of annealing textures in copper and aluminum interconnects based on strain and surface energies. The interconnects, whether they are conventionally or damascene-process fabricated, are subjected to stresses during room temperature or elevated temperature annealing, which, in turn, gives rise to strain energies. The strain energy of a deposit is influenced by its texture and geometry. The annealing texture of an interconnect line is determined such that its elastic strain and surface energies are minimal. The measured textures in damascene-processed copper interconnects and a published result of conventionally processed Al-1%Cu interconnects are discussed based on minimization of their strain and surface energies.     

A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations

The control of leakage power consumption is a growing design challenge for current and future CMOS circuits. Among existing techniques, ‘parking’ a circuit in a minimum leakage state during its standby mode of operation requires minimal circuit modification and results in significant leakage reduction. In this paper we present a heuristic approach (referred to as MLVC) to determine the input vector which minimizes leakage for a combinational design. This approach utilizes approximate signal probabilities of internal nodes to aid in finding the minimum leakage vector. We utilize a probabilistic heuristic to select the next gate to be processed as well as to select the best state of the selected gate. A fast SAT solver is employed to ensure the consistency of the assignments that are made in this process. A variant of MLVC, referred to as MLVC-VAR, is also presented. MLVC-VAR includes the effect of random variations in leakage values due to process, voltage and temperature (PVT) variations. Including the effect of PVT variations for determining minimum leakage vector is crucial because leakage currents have an exponential dependence on power supply, threshold voltage and temperature. To the best of the authors’ knowledge, no other minimum leakage vector determination work has to date included the effect of PVT variations. Experimental results indicate that our MLVC method has very low runtimes, with excellent accuracy compared to existing approaches. Further, the comparison of the mean and standard deviation of the circuit leakage values for MLVC with MLVC-VAR and an existing random vector generating approach proves the need for considering these variations while determining the minimum leakage vector. MLVC-VAR reports, on average, about 9.69% improvement over MLVC with similar runtimes and 5.98% improvement over the random vector generation approach with significantly lower runtimes.     

On the analysis of burst-assembly delay in OBS networks and applications in delay-based service differentiation

In Optical Burst Switching (OBS), packets travel through the network core as part of longer-size optical bursts, which do not suffer electronic conversion until they reach an eggress point. Typically, such optical bursts comprise tens or hundreds of packets, which are assembled/deassembled at border nodes. During the burst-formation process, each arriving packet must wait until the final burst is complete, which clearly adds an extra delay on each packet in the burst, especially on those arriving earlier. However, such burst-assembly delay may be excessive for the appropriate performance of certain applications, mainly real-time interactive ones. This work’s findings are twofold: first, it characterises the burst-assembly delay distribution of each packet in a burst arisen by the main assembly algorithms found in the literature; and, second, it introduces a new burst-assembly strategy that takes into account the particular delay constrains of packets in the formation of optical bursts, along with a detailed study of its properties. This work has been funded by the “Ministerio de Educación y Ciencia” of Spain under grant TEC2006-03246.     

Sensitivity analysis in economics based test strategy planning

This article will present methods to analyze the sensitivity of test costs to the inaccuracy of the individual costing parameters. The results show that a few parameters—e.g., the gate count—need very detailed estimates, whereas the accuracy of many other parameters is insignificant in 99% of all cases. The techniques presented allow an in-depth evaluation of what is perceived as the main drawback in the use of economic modeling methods, namely, the element of risk associated with inaccuracies in the input data.