Stability of N-channel polysilicon thin-film transistors with ECRplasma thermal gate oxide

The effects of electrical stress on n-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) plasma gate oxide have been investigated. The plasma-hydrogenerated low-temperature (⩽600°C) TFT's exhibited very a small increase of threshold voltage (ΔV_th<0.3 V) under the stress conditions (V_gs=15 V, V_ds=0 V ~15 V, and stress time=5×10⁴ s). The ΔV_t h was larger for the stress in the linear region than in the saturation region. It was found that the device degradation for the stress in the saturation region was caused by the hot-carriers. Increase of OFF current was maximum for the stress at V_gs=V_ds while for the stress at V_gsds, degradation of transconductance was the dominant effect seen     

Oxygen Ion Implantation Isolation Planar Process for AlGaN/GaN HEMTs

A multienergy oxygen ion implantation process was demonstrated to be compatible with the processing of high- power microwave AlGaN/GaN high electron mobility transistors (HEMTs). HEMTs that are isolated by this process exhibited gate-lag- and drain-lag-free operation. A maximum output power density of 5.3 W/mm at V_gs = -4 V and V_ds = 50 V and a maximum power added efficiency of 51.5% at V_gs = -4 V and V_ds = 30 V at 3 GHz were demonstrated on HEMTs without field plates on sapphire substrate. This isolation process results in planar HEMTs, circumventing potential problems with enhanced gate leakage due to the gate contacting the 2-D electron gas at the mesa sidewall.     

3.3 V operation GaAs power MESFETs with 65% power-added efficiencyfor hand-held telephones

High-low doped metal semiconductor field effect transistors (MESFETs) operating at a drain bias of 3.3 V have been developed. The MESFETs with 0.6 μm gate length and 12 mm gate width show a maximum drain current density of 310 mA/mm and a uniform transconductance of around 112 mS, ranging from V_gs=-1.8 V to 0.5 V. The device tested at 3.3 V drain bias and 900 MHz demonstrates an output power of 30.9 dBm with associate power-added-efficiency of 65% for an input power of 20 dBm     

High performance 0.1 μm gate-length p-type SiGe MODFET's andMOS-MODFET's

High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (g_m) of 142 mS/mm, a unity current gain cut-off frequency (f_T) of 45 GHz and a maximum oscillation frequency (f_MAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO₂ was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at V_gs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g _m of 90 mS/mm, f_T of 38 GHz, and f_max of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NF_min) of 1.29 dB and an associated power gain (G_a) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF _min of 0.92 dB and a G_a of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications     

Delay time analysis of submicron InP-based HEMT's

The intrinsic delay time of submicron InP-based HEMT's has been evaluated by coupling the delay time analysis with a 2D Ensemble Monte Carlo Simulation. The relationship between the delay time and the transit time is explained. It is shown that the delay time can be quite different from the transit time depending on the velocity modulation. The delay from each segment of the HEMT is calculated to study the distribution of the delay inside the device. The delay from the gate region was the major contributor while that from the drain region was also important. The bias dependence of the delay in each region of the device was calculated to explain the bias dependence of the total intrinsic delay time. The intrinsic delay time increase at low V_gs was due to the increase of τ_d and τ_s and the increase at high V_ds was due to the increase of τd. As a means of validation, the simulated data have been compared with experimental intrinsic delay time data at various bias points. Good agreement was found over a wide V_gs and V _ds range     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

A high performance super self-aligned 3 V/5 V BiCMOS technologywith extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 μm design rules (0.5 μm as one nesting tolerance) has achieved f_l and f_max for npn bipolar (A_e=1×2 μm²) of 23 GHz and 24 GHz at V_ce=3 V, respectively, with BV_ceo⩾5.5 volts, and βV_A product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A_e=1×2 μm² ; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 Å, L_eff=0.6 μm; V_th,nch =0.45 V; V_th,pch=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 μm; gate L_eff=0.7 μm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW     

2.5 dB NF 3.1-10.6 GHz CMOS UWB LNA with small group-delay variation

A 3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay variation is only plusmn 16.7 ps across the whole band) using standard 0.13 mum CMOS technology is reported. To achieve high and flat gain and small group-delay variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA achieved input return loss (S₁₁) of -17.5 to -33.6 dB, output return loss (S₂₂) of -14.4 to -16.3 dB, flat forward gain (S₂₂) of 7.92 plusmn 0.23 dB, and reverse isolation (S₁₂) of -25.8 to -41.9 dB over the 3.1-10.6 GHz band of interest. A state-of-the-art noise figure (NF) of 2.5 dB was achieved at 10.5 GHz.     

A monolithic DC temperature compensation bias scheme for multistageHEMT integrated circuits

This work benchmarks the first demonstration of a multistage monolithic HEMT IC design which incorporates a DC temperature compensated current-mirror bias scheme. This is believed to be the first demonstrated monolithic HEMT bias scheme of its kind. The active bias approach has been applied to a 2-18 GHz five-section low noise HEMT distributed amplifier which achieves a nominal gain of 12.5 dB and a noise figure <2.5 dB across a 2-18 GHz band, The regulated current-mirror scheme achieves better than 0.2% current regulation over a 0-125°C temperature range, The RF gain response was also measured over the same temperature range and showed less than 0.75 dB gain degradation. This results in a -0.006 dB/°C temperature coefficient which is strictly due to HEMT device G_m variation with temperature. The regulated current-mirror circuit can be employed as a stand-alone V_gs-voltage reference circuit which fan be monolithically applied to the gate bias terminal of existing HEMT ICs for providing temperature compensated performance, This monolithic bias approach provides a practical solution to DC bias regulation and temperature compensation for HEMT MMICs which can improve the performance, reliability, and cost of integrated microwave assemblies (IMAs) used in space-flight military applications     

1.1 kV 4H-SiC power UMOSFETs

Silicon Carbide (4H-SiC), power UMOSFETs were fabricated and characterized from room temperature to 200°C. The devices had a 12-μm thick lightly doped n-type drift layer, and a nominal channel length of 4 μm. When tested under Fluorinert^TM at room temperature, blocking voltages ranged from 1.0 kV to 1.2 kV. Effective channel mobility ranged from 1.5 cm²/V.s at room temperature with a gate bias of 32 V (3.5 MV/cm) up to 7 cm²/V.s at 100°C with an applied gate bias of 26 V (2.9 MV/cm). Specific on-resistance (R_on,sp) was calculated to be as low as 74 mΩ.cm² at 100°C under the same gate bias     

Epitaxially-grown GaN junction field effect transistors

Junction field effect transistors (JFETs) are fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition (MOCVD). The dc and microwave characteristics of the device are presented. A junction breakdown voltage of 56 V is obtained corresponding to the theoretical limit of the breakdown field in GaN for the doping levels used. A maximum extrinsic transconductance (g_m ) of 48 mS/mm and a maximum source-drain current of 270 mA/mm are achieved on a 0.8 μm gate JFET device at V_GS=1 V and V_DS=15 V. The intrinsic transconductance, calculated from the measured g_m and the source series resistance, is 81 mS/mm. The f_T and f_max for these devices are 6 GHz and 12 GHz, respectively. These JFET's exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing the current collapse is presented, and an estimate for the length of the trapped electron region is given     

AlSb/InAs HEMT's for low-voltage, high-speed applications

The design, fabrication, and characterization of 0.1 μm AlSb/InAs HEMT's are reported. These devices have an In_0.4Al _0.6As/AlSb composite barrier above the InAs channel and a p ⁺ GaSb layer within the AlSb buffer layer. The HEMT's exhibit a transconductance of 600 mS/mm and an f_T of 120 GHz at V_Ds=0.6 V. An intrinsic f_T of 160 GHz is obtained after the gate bonding pad capacitance is removed from an equivalent circuit. The present HEMT's have a noise figure of 1 dB with 14 dB associated gain at 4 GHz and V_Ds=0.4 V. Noise equivalent circuit simulation indicates that this noise figure is primarily limited by gate leakage current and that a noise figure of 0.3 dB at 4 GHz is achievable with expected technological improvements. HEMT's with a 0.5 μm gate length on the same wafer exhibit a transconductance of 1 S/mm and an intrinsic f_TL_g, product of 50 GHz-μm     

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.     

AlGaN/GaN Metal–Oxide–Semiconductor High-Electron Mobility Transistors Using Oxide Insulator Grown by Photoelectrochemical Oxidation Method

A photoelectrochemical oxidation method was used to directly grow oxide layer on AlGaN surface. The annealed oxide layer exhibited beta-Ga₂O₃ and alpha-Al₂O₃ crystalline phases. Using a photoassisted capacitance-voltage method, a low average interface-state density of 5.1 times 10¹¹ cm^-2. eV^-1 was estimated. The directly grown oxide layer was used as gate insulator for AlGaN/GaN MOS high-electron mobility transistors (MOS-HEMTs). The threshold voltage of MOS-HEMT devices is -5 V. The gate leakage currents are 50 and 2 pA at forward gate bias of VGS = 10 V and reverse gate bias of V_GS = -10 V, respectively. The maximum value of g_m is 50 mS/mm of VGs biased at -2.09 V.     

0.18 μm 21-27 GHz CMOS UWB LNA with 9.3 ± 1.3 dB gain and 103.9 ± 8.1 ps group delay

A 21-27 GHz CMOS ultra-wideband low-noise amplifier (UWB LNA) with state-of-the-art phase linearity property (group delay variation is only ± 8.1 ps across the whole band) is reported for the first time. To achieve high and flat gain (S₂₁) and small group delay variation at the same time, the inductive series peaking technique was adopted in the output of each stage for bandwidth enhancement. The LNA dissipated 27 mW power and achieved input return loss (S₁₁) of 213 to 220.1 dB, output return loss (S₂₂) of 28.2 to 230.2 dB, flat S21 of 9.3 ± 1.3 dB, reverse isolation (S₁₂) of 252.7 to 273.3 dB, and noise figure of 4.9?6.1 dB over the 21-27 GHz band of interest. The measured 1 dB compression point (P_1dB) and input third-order intermodulation point (IIP3) were 214 and 24 dBm, respectively, at 24 GHz.     

Epitaxial lift-off GaAs HEMT's

An extensive study of epitaxial lift-off (ELO) Al_0.3Ga _0.7As/GaAs modulation doped heterostructure high electron mobility field-effect transistors (HEMT's) is presented. Effects of ELO on electron transport properties of two-dimensional electron gas at AlGaAs/GaAs interface are investigated. An ELO HEMT with 1.5 μm gate length had a maximum extrinsic transconductance g_m-max=125 mS/mm, a unity current gain cut-off frequency f_t=10.5 GHz, and a maximum frequency of oscillation f_max=12 GHz. Statistical distributions of maximum intrinsic transconductance of ELO HEMT's are presented and compared with their on-wafer counterparts. Stability of the ELO HEMT's has also been evaluated by continuous operation at room temperature under dc bias     

Separation of hot-carrier-induced interface trap creation and oxidecharge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V_gs stress, HEIP is found to dominate the shift of threshold voltage V_t. When V_gs increases to a moderate value, the V_t shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V_gs is increased further to V_gs=V_ds. For the first time, the effects of interface trap creation and oxide charge trapping on the V_t shift are quantified by the proposed technique     

First demonstration of monolithic InP-based HBT amplifier with PNPactive load

An InP-based integrated HBT amplifier with PNP active load was demonstrated for the first time using complementary HBT technology (CRBT). Selective molecular beam epitaxy (MBE) regrowth was employed and a merged processing technology was developed for the monolithic integration of InP-based NPN and PNP HBTs on the same chip. The availability of PNP devices allowed design of high gain amplifiers with low power supply voltage. The measured amplifier with PNP HBT active load achieved a voltage gain of 100 with a power supply (V_CC) of 1.5 V. The corresponding voltage swing was 0.9 V to 0.2 V. The amplifier also demonstrated S₂₁ of 7.8 dB with an associated S₁₁ and S₂₂ of -9.5 dB and -8.1 dB, respectively, at 10 GHz     

On the SiO2-based gate-dielectric scaling limit forlow-standby power applications in the context of a 0.13 μm CMOS logictechnology

This paper describes a leading-edge 0.13 μm low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I _off) and gate delay (T_d) performance at operating voltages (V_cc) of 1.5 V and 1.2 V, devices with 0.11 μm nominal gate length (L_g-nom) and various gate-oxide thicknesses (T_ox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Å in order to keep acceptable off-state power consumption at V_cc=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T_ox=26 Å) is targeted for V_cc=1.5 V with worst case I_off <10 pA/μm and nominal gate delay 24 ps/gate. Another design, named LP1 (T_ox=22 Å) is targeted for V_cc =1.2 V with worst case I_off<20 pA/μm and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 μA/μm nominal drive currents at V_cc for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm² cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T _ox=22 Å) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125°C and V _cc=1.5 V     

Planar microwave integrated phase-shifter design with high purityferroelectric material

Ferroelectric materials (FEM's) are very attractive because their dielectric constant can be modulated under the effect of an externally applied electric field perpendicular to the direction of propagation of a microwave signal. FEM may be particularly useful for the development of a new family of planar phase shifters which operate up to X-band. The use of FEM in the microwave frequency range has been limited in the past due to the high losses of these materials; tan δ=0.3 at 3 GHz is typical for commercial BaTiO₃ (BTO) and due to the high electric field necessary to bias the structure in order to obtain substantial dielectric constant change. In this paper, a significant reduction in material losses is demonstrated. This is achieved by using a new sol-gel technique to produce barium modified strontium titanium oxide [Ba_1-xSr_xTiO₃ (BST)], which has ferroelectric properties at room temperature. Also demonstrated is how the use of thin ceramics reduces the required bias voltage below 250 V, with almost no power consumption required to induce a change in the dielectric constant. A phase shift of 165° was obtained at 2.4 GHz, with an insertion loss below 3 dB by using a bias voltage of 250 V. Due to the planar geometry and light weight of the device, it can be fully integrated in planar microwave structures