A novel amorphous silicon doping superlattice device with doubleswitching characteristics for multiple-valued logic applications

An amorphous silicon doping superlattice device with different period lengths is developed, providing a double switching characteristic that has been demonstrated to yield multiple stable states for multiple-valued logic applications. Unlike those of conventional switching devices, the switching characteristics of the present device are caused by avalanche multiplication and a barrier-lowering effect. A tristate memory cell using this device is proposed and discussed     

Charge controlled nanosecond logic circuitry

To date, nanosecond circuitry has been based mainly on two devices--the transistor and the tunnel diode. Unfortunately, the speed advantages of the tunnel diode cannot be utilized because the current gain is limited by practical tolerance requirements. Therefore, any circuits designed "around" these two devices are either practical, but limited to the speed of the transistor, or impractical, for general purpose logic, with the speed performance of the tunnel diode. The region of the tunnel diode gain bandwidth curve which is limited by tolerances can be exploited by using a storage diode as an interstage current amplifier or charge transformer. The operation of the storage diode is discussed, and charge gain bandwidth criteria are developed from the physical equations describing the device. Charge control switching curves are developed for the tnnnel diode which define its operation as a charge amplifier. The combination of tunnel diode and charge transformer (TDCT Logic) enables a wide variety of logic functions to be obtained with a gain bandwidth tolerance performance previously unattainable in nanosecond logic circuitry. To demonstrate this capability a novel "NOR" circuit is described and a worse case analysis of the fan out tolerance performance is given in the Appendix.     

MNOS LSI memory device data retention measurements and projections

The retention characteristics of an MNOS LSI memory device are interpreted from the properties of its basic MNOS transistor. A technique is developed for measuring and predicting retention properties of large quantity device lots. A production lot test method for determining the 10 000-h data retention properties of LSI memory devices is proposed. Also included in the paper are measured failure rates, identifying the retention failures and reliability for a specific LSI memory device.     

Advancements in bipolar VLSI circuits and technologies

Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic and emitter-coupled logic are still mostly used, but new circuit technologies such as integrated injection logic or merged transistor logic and Schottky transistor logic or integrated Schottky logic have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly being replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected through technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 /spl mu/m dimensions or below.     

一种新型高速嵌入式动态随机存储器

基于二维器件模拟工具,研究了一种采用栅控二极管作为写操作单元的新型平面无电容动态随机存储器.该器件由一个n型浮栅MOSFET和一个栅控二极管组成.MOSFET的p型掺杂多晶硅浮栅作为栅控二极管的p型掺杂区,同时也是电荷存储单元.写“0”操作通过正向偏置二极管实现,而写“1”操作通过反向偏置二极管,同时在控制栅上加负电压使栅控二极管工作为隧穿场效应晶体管(Tunneling FET)来实现.由于正向偏置二极管和隧穿晶体管开启时接近1μA/μm的电流密度,实现了高速写操作过程,而且该器件的制造工艺与闪烁存储器和逻辑器件的制造兼容,因此适合在片上系统(SOC)中作为嵌入式动态随机存储器使用.     

用硅光电负阻器件产生光学双稳态

本文利用作者近期研制出的硅光电表面负阻晶体管（PNEGIT），首次提出并通过实验成功地实现了一种新的光学双稳态即以PNEGIT作为光输入器件，用它驱动一发光管（LED）作为光输出器件，由于PNEGIT具有负阻输出特性，致使LED输出光功率（POUt）一输入光功率（Pin）特性上出现光学双稳环．这种器件具有光开关、光逻辑、光存贮等多种功能，将为硅光电器件在光信息处理、光计算、光通讯等领域中的应用，开辟一条新途径     

Novel single quantum well optoelectronic devices based on exciton bleaching

Novel planar high-speed optoelectronic devices offering advantages for optoelectronic integration are proposed. Exciton-resonant light propagates along a single-mode rib waveguide containing a single quantum well (SQW), the only absorbing medium in the waveguide. The two-dimensional (2D) excitonic optical absorption is controlled by the bleaching effect induced by free carriers, whose electrical conduction simultaneously makes possible optical detection and high-speed transistor action. Three such optical modulating devices are: 1) a gate-controlled single quantum well field-effect transistor (FET) optical modulator (FETOM), 2) an optically-readable memory element, and 3) an optically-switched charge storage device. The FETOM, in which the free-carrier density in the SQW is controlled by the gate voltage, offers high speed (22 ps), small size (125 μm), and unique potential for optoelectronic integration.     

Low-voltage MOBILE logic module based on Si/SiGe interbandtunnelling diodes

Si/SiGe interband tunnelling diodes have been grown by MBE on high resistivity (n^-) silicon substrates. The device enables a very low voltage, high-speed logic on a silicon substrate. A novel self-aligned diode is processed using optical lithography and dopant-selective wet chemical etching. A maximum speed index for a 60 μm² anode area device is evaluated to 2.2 ns/V resulting in a switching speed of 0.5 ns. A logic latch built of two series connected diodes (MOBILE principle) is demonstrated, showing very robust logic operation at a supply voltage as low as 0.3 V. The used technology may be employed for a co-integration with both SiGe heterostructure bipolar- and field-effect transistor technology and may contribute to future low-voltage high speed logic on Si substrates     

Effect of a buffer layer in the epi-substrate region to boost the avalanche capability of a 100V Schottky diode

The aim of this paper is to give an insight and a possible explanation of the limitations in the Reverse Bias Safe Operating Area of 100V Si Power Schottky Diodes. Starting from experiments and going through device simulations and theory a physical explanation of device failure both in short (i.e. isothermal) and long pulse are explained. With the help of the theoretical analysis an improvement of the design is proposed to increase avalanche capability of these devices and preliminary experimental data are reporting a very promising increase of both the maximum sustainable current in avalanche condition and the maximum sustainable avalanche energy in UIS conditions.     

A comparison of semiconductor devices for high-speed logic

The bipolar transistor and FET are compared, considering both today's most advanced implementations and "ultimate" scaled-down devices. The differences between the devices are quantified in terms of transconductance and intrinsic speed. Old limits are re-examined and ways of extending the devices toward their ultimate in performance are proposed. While the major emphasis is on silicon, a comparison is made with the GaAs MESFET. Other semiconductor devices are discussed in the context of "bipolar-like" and "FET-like" devices, and the HEMT is considered a very promising candidate for high-speed logic. While Josephson junction logic is not discussed at length, it is a continual point of reference. In addition to comparing devices, the on-chip wiring environment is discussed, especially concerning its impact on power-delay products.     

The potential of diamond and SiC electronic devices for microwaveand millimeter-wave power applications

The potential of SiC and diamond for producing microwave and millimeter-wave electronic devices is reviewed. It is shown that both of these materials possess characteristics that may permit RF electronic devices with performance similar to or greater than what is available from devices fabricated from the commonly used semiconductors, Si, GaAs, and InP. Theoretical calculations of the RF performance potential of several candidate high-frequency device structures are presented: the metal semiconductor field-effect transistor (MESFET), the impact avalanche transit-time (IMPATT) diode, and the bipolar junction transistor (BJT). Diamond MESFETs are capable of producing over 200 W of X-band power as compared to about 8 W for GaAs MESFETs. Devices fabricated from SiC should perform between these limits. Diamond and SiC IMPATT diodes also are capable of producing improved RF power compared to Si, GaAs, and InP devices at microwave frequencies. RF performance degrades with frequency and only marginal improvements are indicated at millimeter-wave frequencies. Bipolar transistors fabricated from wide bandgap material probably offer improved RF performance only at UHF and low microwave frequencies     

盖革模式雪崩光电二极管的场效应管淬灭电路设计

雪崩光电二极管(Avalanche Photondiode,APD)是一种常用于激光探测领域的光敏元件.本文针对盖革模式雪崩光电二极管(Geiger Mode-Avalanche Photondiode,Gm-APD)工作时发生的雪崩效应,设计了一种场效应管淬灭电路(Field Effect Transistor Qu...     

Negative Differential Resistance Circuit Design and Memory Applications

Based on a circuit point of view, a high-performance negative differential resistance (NDR) element is designed and a possible compact device implementation is presented. The NDR structure exhibits ultrahigh peak-to-valley current ratio and also high switching speed. The corresponding process and design are completely compatible with contemporary Si CMOS technology, as they rely on coupled transistor structures. A single-NDR element static-random-access-memory cell prototype with a compact size and high speed is proposed as an interesting application suitable for embedded memory.      

A new MNOS memory element—the tunnel diode

MNOS (Metal-Nitride-Oxide-Silicon) memory devices commercially available today consist of transistor arrays where each device represents a memory bit. Typical devices have densities greater than 8 K bits and are generally manufactured on epitaxial based processes for isolation. The state of each bit is determined by its threshold voltage and is sensed by interpreting if the transistor is in the “off” or “on” condition. A new MNOS memory element is described where detection of junction tunnelling current is used as the sense mechanism. Substrate forms the “third” terminal and the element has the possibility of being the basis of a dense array. The technique can be developed in p or n channel and can be used as an add-on to volatile random access memories.     

Why is nonvolatile ferroelectric memory field-effect transistorstill elusive?

In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed     

Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

Quantum-effect devices utilizing resonant tunneling are promising candidates for future nano-scale integration. Originating from the technological progress of semiconductor technology, circuit architectures with reduced complexity are investigated by exploiting the negative-differential resistance of resonant tunneling devices. In this paper a resonant tunneling device threshold logic family based on the Monostable-Bistable Transition Logic Element (MOBILE) is proposed and applied to different parallel adder designs, such as ripple carry and binary carry lookahead adders. The basic device is a resonant tunneling transistor (RTT) composed of a resonant tunneling diode monolithically integrated on the drain contact layer of a heterostructure field effect transistor. On the circuit level the key components are a programmable NAND/NOR logic gate, threshold logic gates, and parallel counters. The special properties of MOBILE logic gates are considered by a bit-level pipelined circuit style. Experimental results are presented for the NAND/NOR logic gate.     

A novel 2-T structure memory device using a Si nanodot for embedded application

Performance and reliability of a 2 transistor Si nanocrystal nonvolatile memory(NVM) are investigated. A good performance of the memory cell has been achieved,including a fast program/erase(P/E) speed under low voltages,an excellent data retention(maintaining for 10 years) and good endurance with a less threshold voltage shift of less than 10%after 10~4 P/E cycles.The data show that the device has strong potential for future embedded NVM applications.     

Theory of a new three-terminal microwave power amplifier

The feasibility of a new three-terminal linear power amplifier has been demonstrated both theoretically and experimentally from 0.5 to 3.0 GHz. The new amplifier is similar to an n-p-n bipolar transistor in configuration but develops extra power gain through avalanche multiplication and by the use of transit time in the collector. Major differences in the construction of the two devices are in their collector doping profiles and depletion layer widths. It is estimated that this new amplifier will be capable of several watts of power output at 10 GHz with useful gain, good linearity, and wide dynamic range. An acronym, CATT, which stands for controlled avalanche transit-time triode, is used to designate this new microwave semiconductor device. In this paper, the theory of the CATT is developed. It is found to be dc and RF stable. The necessary conditions on the ionization coefficients for signal amplification are investigated. The emitter-base dynamics of the CATT are shown to be quite different from a transistor due to hole feedback from the avalanche multiplication region. This phenomena results in a more uniform emitter current injection and better use of the emitter finger area than for transistors.     

Operation of a novel negative differential conductance transistorfabricated in a strained Si quantum well

The operation of a negative differential conductance (NDC) transistor fabricated on a high-mobility Si/Si_1-xGe_x heterostructure wafer is described. The drain characteristic of this device shows a large NDC with current peak-to-valley ratios as high as 600 (100) at T=0.4 K (T=1.3 K). The NDC can be modulated over a wide range of current levels by either of two separately-contacted gate electrodes. The device shows bistable switching behaviour in both current- and voltage-controlled circuit configurations. The novel operating principle of this transistor is described, along with its potential for future logic and memory applications     

Double-drift avalanche photodetectors

A new avalanche photodiode device is proposed that has superior noise and bandwidth performance. This structure incorporates a drift region on both sides of the high field avalanche region. With the proper design, this reduces the capacitance by nearly a factor of two, without degrading the transit-time limited speed. In fact, it is shown that the double-drift structure ran actually improve the intrinsic device speed. It is also shown that for high speed devices in which the layers must be kept thin, it can be advantageous to absorb light on both sides of the avalanche region, in spite of the consequent increase in the excess noise factor