Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

Dopant-Segregated Schottky Silicon-Nanowire MOSFETs With Gate-All-Around Channels

In this letter, we demonstrated dopant-segregated Schottky (DSS) p-MOSFET with gate-all-around silicon-nanowire (SiNW) channel of 10 nm in diameter. The DSS transistor shows improved performance as compared to a reference Schottky barrier (SB) transistor without dopant segregation. The DSS transistor shows $I_{rm ON}$ of 319 $mu hbox{A}/muhbox{m}$ at a low gate overdrive of $-$ 0.6 V, high $I_{rm ON}/I_{rm OFF}$ ratio $(sim!hbox{10}^{5})$, and short-channel performance with subthreshold slope $sim$90 mV/dec down to 100-nm gate length with relatively thick (6 nm) deposited gate oxide. The DSS transistor also shows significant reduction ( $sim!hbox{40}times$ lower) in the series resistance as compared to the SB transistor. The origin of the improved performance of the DSS is the thin dopant layer segregated at the nickel monosilicide/SiNW point contact which results in the enhanced hole injection at the source side and the suppressed electron injection at the drain side.      

N-Channel MOSFETs With Embedded Silicon–Carbon Source/Drain Stressors Formed Using Cluster-Carbon Implant and Excimer-Laser-Induced Solid Phase Epitaxy

In this letter, we report the use of a novel cluster-carbon $(hbox{C}_{7} hbox{H}_{7}^{+})$ implant and pulsed-excimer-laser-induced solid-phase-epitaxy technique to form embedded silicon–carbon (Si:C) source/drain (S/D) stressors. A substitutional carbon concentration $C_{rm sub}$ of $sim$ 1.1% was obtained in this letter. N-channel MOSFETs (n-FETs) integrated with embedded silicon–carbon (Si:C) S/D stressors formed using the novel cluster-carbon implant and pulsed-laser-anneal technique demonstrate improvement in current drive of 14% over control n-FETs formed with Si preamorphization implant. $I_{rm OFF}{-}I_{rm DSAT}$ comparison shows a 15% $I_{rm DSAT}$ enhancement for n-FETs with embedded Si:C S/D at an $I_{rm OFF} = hbox{1} hbox{nA}/muhbox{m}$ despite a slightly higher series resistance.      

Schottky Barrier Height Modulation of Nickel–Dysprosium-Alloy Germanosilicide Contacts for Strained P-FinFETs

This letter reports on the fabrication and hole Schottky barrier $(Phi_{ rm B}^{rm p})$ modulation of a novel nickel (Ni)–dysprosium (Dy)-alloy germanosilicide (NiDySiGe) on silicon–germanium (SiGe). Aluminum (Al) implant is utilized to lower the $Phi_{rm B}^{rm p}$ of NiDySiGe from $sim$0.5 to $sim$ 0.12 eV, with a correspondingly increasing Al dose in the range of $ hbox{0}$–$hbox{2}timeshbox{10}^{15} hbox{atoms}/ hbox{cm}^{2}$. When integrated as the contact silicide in p-FinFETs (with SiGe source/drain), NiDySiGe with an Al implant dose of $hbox{2}timeshbox{10}^{14} hbox{atoms}/ hbox{cm}^{2}$ leads to 32% enhancement in $I_{rm DSAT}$ over p-FinFETs with conventional NiSiGe contacts. Ni–Dy-alloy silicide is a promising single silicide solution for series-resistance reduction in CMOS FinFETs.      

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Newly proposed mobility-booster technologies are demonstrated for metal/high- $k$ gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/$ hbox{HfO}_{2}$ gate stacks with $T_{rm inv} = hbox{1.4} hbox{nm}$ on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using $hbox{HfSi}_{x}/hbox{HfO}_{2}$ gate stacks with $T_{rm inv} = hbox{1.4} hbox{nm}$. High-performance n- and pFETs are achieved with $I_{rm on} = hbox{1300}$ and 1000 $muhbox{A}/muhbox{m} hbox{at} I_{rm off} = hbox{100} hbox{nA}/mu hbox{m}$, $V_{rm dd} = hbox{1.0} hbox{V}$, and a gate length of 40 nm, respectively.      

First Internal Spacers' Introduction in Record High $I_{rm ON}/I_{rm OFF} hbox{TiN/HfO}_{2}$ Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic $CV/I$ delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent $I_{rm ON}/I_{rm OFF}$ characteristics (NMOS: 2.33 $hbox{mA}/muhbox{m}$ at 27 $hbox{pA}/muhbox{m}$ and PMOS: 1.52 $hbox{mA}/muhbox{m}$ at 38 $hbox{pA}/muhbox{m}$). A gate capacitance $C_{rm gg}$ reduction of 32% is measured, thanks to $S$-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain $A_{rm VI}(= g_{m}/g_{rm ds})$ is improved by 92%.      

AlN/GaN Insulated-Gate HEMTs With 2.3 A/mm Output Current and 480 mS/mm Transconductance

High-electron mobility transistors (HEMTs) based on ultrathin AlN/GaN heterostructures with a 3.5-nm AlN barrier and a 3-nm $hbox{Al}_{2}hbox{O}_{3}$ gate dielectric have been investigated. Owing to the optimized AlN/GaN interface, very high carrier mobility $(sim!!hbox{1400} hbox{cm}^{2}/hbox{V}cdothbox{s})$ and high 2-D electron-gas density $(sim!!kern1pthbox{2.7} times hbox{10}^{13} /hbox{cm}^{2})$ resulted in a record low sheet resistance $(sim !!hbox{165} Omega/hbox{sq})$. The resultant HEMTs showed a maximum dc output current density of $simkern1pt$2.3 A/mm and a peak extrinsic transconductance $g_{m,{rm ext}} sim hbox{480} hbox{mS/mm}$ (corresponding to $g_{m,{rm int}} sim hbox{1} hbox{S/mm}$). An $f_{T}/f_{max}$ of 52/60 GHz was measured on $hbox{0.25} times hbox{60} muhbox{m}^{2}$ gate HEMTs. With further improvements of the ohmic contacts, the gate dielectric, and the lowering of the buffer leakage, the presented results suggest that, by using AlN/GaN heterojunctions, it may be possible to push the performance of nitride HEMTs to current, power, and speed levels that are currently unachievable in AlGaN/GaN technology.      

Multi-Channel Field-Effect Transistor (MCFET)—Part I: Electrical Performance and Current Gain Analysis

Multi-Channel Field-Effect Transistor (MCFET) structures with ultralow $I_{ rm OFF}$ (16 $hbox{pA}/muhbox{m}$) and high $I_{rm ON}$ (N: 2.27 $ hbox{mA}/muhbox{m}$ and P: 1.32 $hbox{mA}/muhbox{m}$ ) currents are obtained on silicon on insulator (SOI) with a high-$ kappa$/metal gate stack, satisfying both low-standby-power and high-performance requirements. The experimental current gain of the MCFET structure is compared with that of an optimized planar FD-SOI reference with the same high-$kappa$/metal gate stack and is quantitatively explained by an analytical model. Transport properties are investigated, and the specific MCFET electrostatic properties are evidenced, in particular a higher $V_{rm Dsat}$ for MCFETs compared with the planar reference. Finally, through 3-D numerical simulations correlated with specific characterizations, the influence of the channel width on the electrical performance is analyzed. For narrow devices, the parasitic bottom channel increases the total drain current of the MCFET structure without degrading the electrostatic integrity.      

Work-Function Engineering for 32-nm-Node pMOS Devices: High-Performance TaCNO-Gated Films

We have demonstrated p-type field effect transistors (p-FETs) devices using a TaCNO metal gate for the first time. These p-FETs have threshold voltage values of $-$ 0.4 and $-$ 0.25 V for HfSiON and HfSiO gate dielectrics, respectively, with equivalent oxide thickness of 1.6–1.7 nm. The TaCNO metal shows a high effective work function (eWF) of 4.89 eV on thick $hbox{SiO}_{2}$ interface layer, although the eWF rolls off with reducing EOT. Excellent transistor characteristics are achieved, with $I_{rm on}$ of $hbox{375} muhbox{A}/muhbox{m}$ at $I_{rm off} = hbox{60 nA}$, for $V_{rm dd} = hbox{1.1} hbox{V}$ .      

Performance Benefits of Diamond-like Carbon Liner Stressor in Strained P-Channel Field-Effect Transistors With Silicon–Germanium Source and Drain

We report the first investigation of the impact of diamond-like carbon (DLC) high-stress liner on strained p-channel metal–oxide–semiconductor field-effect transistors (p-FETs) having silicon–germanium (SiGe) source-and-drain (S/D) stressor. The DLC exhibited a very high compressive stress of $sim$5 GPa. At a fixed $I_{ rm off}$ of $hbox{1}times hbox{10}^{-7} hbox{A}/mu hbox{m}$, the DLC liner stressor contributed to a further 11% $I_{rm on}$ enhancement for p-FETs with $hbox{Si}_{0.75} hbox{Ge}_{0.25}$ S/D. This is the first demonstration that further boost in device performance in a p-FET that is already strained using $hbox{Si}_{0.75}hbox{Ge}_{0.25}$ S/D can be achieved with DLC liner stressor. Due to the extremely high intrinsic compressive stress of the DLC, a very small DLC thickness of $sim$27 nm is sufficient for achieving significant strain effect and performance enhancement.      

High-Density and Low-Leakage-Current MIM Capacitor Using Stacked $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Insulators

We have fabricated high-$kappa hbox{Ni}/hbox{TiO}_{2}/hbox{ZrO}_{2}/ hbox{TiN}$ metal–insulator–metal (MIM) capacitors. A low leakage current of $hbox{8} times hbox{10}^{-8} hbox{A/cm}^{2}$ at 125 $^{circ}hbox{C}$ was obtained with a high 38- $hbox{fF}/muhbox{m}^{2}$ capacitance density and better than the $hbox{ZrO}_{2}$ MIM capacitors. The excellent device performance is due to the lower electric field in 9.5-nm-thick $hbox{TiO}_{2}/ hbox{ZrO}_{2}$ devices to decrease the leakage current and to a higher $kappa$ value of 58 for $ hbox{TiO}_{2}$ as compared with that of $hbox{ZrO}_{2}$ to preserve the high capacitance density.      

Integrated Hydrogen-Sensing Amplifier With GaAs Schottky-Type Diode and InGaP–GaAs Heterojunction Bipolar Transistor

New hydrogen-sensing amplifiers are fabricated by integrating a GaAs Schottky-type hydrogen sensor and an InGaP–GaAs heterojunction bipolar transistor. Sensing collector currents ( $I_{rm CN}$ and $I_{rm CH}$) reflecting to $hbox{N}_{2}$ and hydrogen-containing gases are employed as output signals in common-emitter characteristics. Gummel-plot sensing characteristics with testing gases as inputs show a high sensing-collector-current gain $(I_{rm CH}/I_{rm CN})$ of $≫hbox{3000}$. When operating in standby mode for in situ long-term detection, power consumption is smaller than 0.4 $muhbox{W}$. Furthermore, the room-temperature response time is 85 s for the integrated hydrogen-sensing amplifier fabricated with a bipolar-type structure.      

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

A Center-Offset Polycrystalline-Silicon Thin-Film Transistor With ${rm n}^{+}$ Amorphous-Silicon Contacts

We have studied a bottom-gate polycrystalline-silicon thin-film transistor (poly-Si TFT) with amorphous-silicon (a-Si) ${rm n}^{+}$ contacts and center-offset gated structure, where intrinsic poly-Si is used in the center-offset region. The fabrication process is compatible with the conventional a-Si TFT with addition of thermal annealing for crystallization of a-Si. The bottom-gate poly-Si TFT with a 5-$muhbox{m}$ offset length exhibited a field-effect mobility of 18.3 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and minimum OFF-state current of $hbox{2.79} times hbox{10}^{-12} hbox{A}/muhbox{m}$ at $V_{rm ds} = hbox{5} hbox{V}$. The leakage currents are two orders of magnitude lower than those of a nonoffset TFT with mobility drop from 23.8 to 18.3 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$.      

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

N-Face GaN/AlGaN HEMTs Fabricated Through Layer Transfer Technology

We present a new method to fabricate N-face GaN/AlGaN high electron mobility transistors (HEMTs). These devices are extremely promising for ultrahigh frequency applications where low contact resistances and excellent carrier confinement are needed. In this letter, the N-face of a Ga-face AlGaN/GaN epilayer grown on Si(111) is exposed by removing the Si substrate. To provide mechanical support, prior to the substrate removal, the Ga-face of the wafer is bonded to a Si(100) carrier wafer. The resultant N-face GaN/AlGaN heterostructures exhibited record transport properties ($mu_{e} !=! hbox{1670} hbox{cm}^{2}/hbox{V}cdot hbox{s}$, $n_{s} !=! hbox{1.6} !times! hbox{10}^{13}/ hbox{cm}^{2}$, and $R_{rm sh} = hbox{240} Omega/hbox{sq}$ ). These excellent transport properties rendered N-face HEMTs with 30% higher maximum drain current than Ga-face HEMTs and good RF characteristics ($f_{T} = hbox{10.7} hbox{GHz} cdot muhbox{m}$ and $f_{max} = hbox{21.5} hbox{GHz}cdot muhbox{m}$), comparable to state-of-the-art Ga-face devices.      

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

GaAs MESFET With a High-Mobility Self-Assembled Planar Nanowire Channel

We demonstrate the first metal–semiconductor field-effect transistor with a self-assembled planar $langlehbox{110}rangle$ GaAs nanowire channel. Well-defined dc output and transfer characteristics have been observed with a subthreshold slope of $sim$150 mV/dec, maximum $g_{m}$ of 23 mS/mm, and excellent on-current saturation. Bulklike mobility of $sim! hbox{4100} hbox{cm}^{2}/hbox{V}cdot hbox{s}$ with corresponding electron concentration of $hbox{2.3} cdot hbox{10}^{17} hbox{cm}^{-3}$ is derived by fitting the experimental data using a self-consistent long channel field effect device model.